lh7a400_aci.h

sharp触摸屏测试代码

/**********************************************************************
 *  $Workfile:   LH7A400_aci.h  $
 *  $Revision:   1.1  $
 *  $Author:   MaysR  $
 *  $Date:   Jun 20 2002 10:42:28  $
 *
 *	Project: LH7A400 headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for LH7A400 component:
 *          Audio Codec Interface
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *  $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/LH7A400_aci.h-arc  $
 * 
 *    Rev 1.1   Jun 20 2002 10:42:28   MaysR
 * Removed rouge semi-colons.
 * 
 *    Rev 1.0   Jun 19 2002 17:45:20   MaysR
 * Initial revision.
 * 
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_ACI_H
#define LH7A400_ACI_H

#include "SMA_types.h"

/* ACI Register Structure */ 

typedef struct 
{
    volatile UNS_32   aci_data_reg;  /* Data register */ 
    volatile UNS_32   aci_ctrl_reg;  /* Control register */ 
    volatile UNS_32   aci_stat_reg;  /* Status register */
    volatile UNS_32   aci_eoi_reg;   /* End Of Interrupt register */
    volatile UNS_32   clk_divide;    /* Clock Divide register */
} ACIREGS;

/**********************************************************************
 * Data Register Bit Field 
 *********************************************************************/ 
#define ACI_DATA_REG(n)             _SBF(0, (n & 0xFF))

/**********************************************************************
 * Control Register Bit Fields
 *********************************************************************/ 
#define ACI_TX_ENABLE               _BIT(0)
#define ACI_RX_ENABLE               _BIT(1)
#define ACI_RX_INT_ENABLE           _BIT(2)
#define ACI_TX_INT_ENABLE           _BIT(3)
#define ACI_LOOPBACK_ENABLE         _BIT(4)
#define ACI_TXFE_STOP_CLK_ENABLE    _BIT(5)

/**********************************************************************
 * Status Register Bit Fields
 *********************************************************************/ 
#define ACI_RX_FIFO_EMPTY           _BIT(0)
#define ACI_TX_FIFO_FULL            _BIT(1)
#define ACI_RX_FIFO_FULL            _BIT(2)
#define ACI_TX_FIFO_EMPTY           _BIT(3)
#define ACI_RX_INT_STATUS           _BIT(4)
#define ACI_TX_INT_STATUS           _BIT(5)
#define ACI_RX_BUSY                 _BIT(6)
#define ACI_TX_BUSY                 _BIT(7)

/**********************************************************************
 * Clock Divider Register Bit Field
 *********************************************************************/ 
#define ACI_CLK_DIV(n)              _SBF(0, (n & 0x3FF))


#endif /* LH7A400_ACI_H */