lh7a400_smc.h

sharp触摸屏测试代码

/**********************************************************************
 *	$Workfile:   LH7A400_smc.h  $
 *	$Revision:   1.5  $
 *	$Author:   MaysR  $
 *	$Date:   Aug 27 2002 11:15:04  $
 *
 *	Project: LH7A400 headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for the LH7A400 component:
 *      	Static Memory Controller 
 *
 *	Revision History:
 *	$Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/lh7a400_smc.h-arc  $
 * 
 *    Rev 1.5   Aug 27 2002 11:15:04   MaysR
 * Removed BCR bit reference to RBLE bit.  This bit does not exist
 * in the LH7A400.
 * 
 *    Rev 1.4   Apr 02 2002 12:11:54   SuryanG
 * Made structure definition comply with coding standards.
 * 
 *    Rev 1.3   Apr 02 2002 10:24:28   SuryanG
 * Converted to SMA types.
 * 
 *    Rev 1.2   Apr 02 2002 10:06:28   SuryanG
 * Added legal disclaimer.
 * 
 *    Rev 1.1   Feb 06 2002 17:49:34   BarnettH
 * Removed PACKED
 * 
 *    Rev 1.0   Oct 04 2001 14:32:42   BarnettH
 * Initial revision.
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#if !defined(LH7A400_SMC_H)
#define LH7A400_SMC_H

#include "SMA_types.h"

/**********************************************************************
 * Static Memory Controller Module Register Structure
 *********************************************************************/
typedef struct
{
    volatile UNS_32   bcr0;       /* Configuration for bank 0 */ 
    volatile UNS_32   bcr1;       /* Configuration for bank 1 */ 
    volatile UNS_32   bcr2;       /* Configuration for bank 2 */ 
    volatile UNS_32   bcr3;       /* Configuration for bank 3 */ 
    volatile UNS_32   reserved1;
    volatile UNS_32   reserved2;
    volatile UNS_32   bcr6;       /* Configuration for bank 6 */ 
    volatile UNS_32   bcr7;       /* Configuration for bank 7 */ 
    volatile UNS_32   pc1_attribute;  /* PC1 Attribute */ 
    volatile UNS_32   pc1_common;     /* PC1 Common */ 
    volatile UNS_32   pc1_io;         /* PC1 IO */ 
    volatile UNS_32   reserved3;
    volatile UNS_32   pc2_attribute;  /* PC2 Attribute */ 
    volatile UNS_32   pc2_common;     /* PC2 Common */ 
    volatile UNS_32   pc2_io;         /* PC2 IO */ 
    volatile UNS_32   reserved4;
    volatile UNS_32   pcmcia_control; /* PCMCIA Control*/ 
} SMCREGS;

/**********************************************************************
 * SMC Bank Configuration Register Bit Fields
 *********************************************************************/
#define SMC_BCR_IDCY(n) _SBF(0,((n)&0x0F))  /* Idle Cycle Time */
#define SMC_BCR_WST1(n) _SBF(5,((n)&0x1F))  /* Wait State 1 */
#define SMC_BCR_WST2(n) _SBF(11,((n)&0x1F)) /* Wait State 2 */
#define SMC_BCR_WPERR   _BIT(25)            // Write Protect Error Flag
#define SMC_BCR_WP      _BIT(26)            /* Write Protect */
#define SMC_BCR_PME     _BIT(27)            /* Page Mode Enable */
#define SMC_BCR_MW8     _SBF(28,0)          /* Memory width 8 bits */
#define SMC_BCR_MW16    _SBF(28,1)          /* Memory width 16 bits */
#define SMC_BCR_MW32    _SBF(28,2)          /* Memory width 32 bits */

/**********************************************************************
 * PCMCIA Attribute, Common, and IO Space Configuration Register
 * Bit Fields
 *********************************************************************/
#define PCMCIA_CFG_PC(n)    _SBF(0,((n)&0xFF))  /* Pre-charge delay*/ 
#define PCMCIA_CFG_HT(n)    _SBF(8,((n)&0x0F))  /* Hold time */ 
#define PCMCIA_CFG_AC(n)    _SBF(16,((n)&0xFF)) /* Access time */ 
#define PCMCIA_CFG_W8       _SBF(31,0)  /* Address space 8 bits wide */ 
#define PCMCIA_CFG_W16      _SBF(31,1)  /* Address space 16 bits wide */ 

/**********************************************************************
 * PCMCIA Control Register Bit Fields
 *********************************************************************/
#define PCMCIA_CONTROL_NONE     _SBF(0,0)   /* No cards enabled */ 
#define PCMCIA_CONTROL_CF       _SBF(0,1)   /* One CF enabled */ 
#define PCMCIA_CONTROL_PC       _SBF(0,2)   /* One PC enabled */ 
#define PCMCIA_CONTROL_CFPC     _SBF(0,3)   /* One CF and one PC enabled */ 
#define PCMCIA_CONTROL_PC1RST   _SBF(2,1)   /* Reset card 1 */ 
#define PCMCIA_CONTROL_PC1NORMAL    _SBF(2,0)   /* Normal op card 1 */ 
#define PCMCIA_CONTROL_PC2RST   _SBF(3,1)   /* Reset card 2 */ 
#define PCMCIA_CONTROL_PC2NORMAL    _SBF(3,0)   /* Normal op card 1 */ 
#define PCMCIA_CONTROL_WEN1     _SBF(4,1)   /* Wait State Enable card 1 */ 
#define PCMCIA_CONTROL_WEN2     _SBF(5,1)   /* Wait State Enable card 1 */ 
#define PCMCIA_CONTROL_MANPREG  _SBF(8,1)   /* Manual nPREG */ 
#define PCMCIA_CONTROL_AUTOPREG _SBF(8,0)   /* Auto nPREG */ 

#endif /* LH7A400_SMC_H */