lh7a400_dmac.h

sharp触摸屏测试代码

/**********************************************************************
 *	$Workfile:   lh7a400_dmac.h  $
 *	$Revision:   1.2  $
 *	$Author:   SuryanG  $
 *	$Date:   Apr 01 2002 17:12:06  $
 *
 *	Project: LH7A400 IP headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for the LH7A400 component:
 *      	DMA Controller
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *	$Log:   P:/PVCS6_6/archives/SOC/IP/LH7A400 IP/lh7a400_dmac.h-arc  $
 * 
 *    Rev 1.2   Apr 01 2002 17:12:06   SuryanG
 * Added legal disclaimer.
 * 
 *    Rev 1.1   Jan 08 2002 14:38:32   SuryanG
 * Modified DMACHANNELREGS structure to avoid compiler 
 * warning about missing type specification.
 * 
 *    Rev 1.0   Oct 04 2001 15:27:14   BarnettH
 * Initial revision.
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_DMAC_H
#define LH7A400_DMAC_H

#include "SMA_types.h"

/***********************************************************************
 * DMAC Module Register Structures
 **********************************************************************/ 

 /* The following structure declaration allows referencing the status
  * register either by bit field or by 32-bit register.
  * This allows any of the following constructs to be used, to retrieve
  * the currentstate bit field for example, once DMAC is defined properly,
  * e.g., #define DMAC ((DMACREGS *)(DMAC_REGS_BASE)):
  *
  * tmp = DMAC->usbrx.status.bf.currentstate; 
  * or
  * tmp = DMAC_CURRENTSTATE(DMAC->usbrx.status.r);
  * or
  * tmp = (DMAC->usbrx.status.r & 0x30) >> 4;
  */ 
typedef struct 
{
	volatile UNS_32   control;		/* Control */ 
	volatile UNS_32   interrupt;		/* Interrupt */ 
	volatile UNS_32   reserved1;
	union
	{
		struct
		{
			volatile UNS_32 stall : 1;
			volatile UNS_32 nfb : 1;
			const UNS_32 : 1;
			volatile UNS_32 cherror : 1;
			volatile UNS_32 currentstate : 2;
			volatile UNS_32 nextbuffer : 1;
			volatile UNS_32 bytes : 5;
			const UNS_32 :	0;
		} bf;
		volatile UNS_32 r;
	} status; /* Status */ 
	volatile UNS_32   reserved2;
	volatile UNS_32   remain;			/* Bytes Remaining */ 
	volatile UNS_32   reserved3[2];
	volatile UNS_32   maxcnt0;		/* Maximum byte count */ 
	volatile UNS_32   base0;			/* Base Address */ 
	volatile UNS_32   current0;		/* Current Address */ 
	volatile UNS_32   reserved4;
	volatile UNS_32   maxcnt1;		/* Maximum byte count */ 
	volatile UNS_32   base1;			/* Base Address */ 
	volatile UNS_32   current1;		/* Current Address */ 
	volatile UNS_32   reserved5;
} DMACHANNELREGS;

typedef struct 
{
	DMACHANNELREGS	usbrx;
	DMACHANNELREGS	usbtx;
	DMACHANNELREGS	mmcrx;
	DMACHANNELREGS	mmctx;
	DMACHANNELREGS	reserved0[4];
	DMACHANNELREGS	aacrx0;
	DMACHANNELREGS	aactx0;
	DMACHANNELREGS	aacrx1;
	DMACHANNELREGS	aactx1;
	DMACHANNELREGS	aacrx2;
	DMACHANNELREGS	aactx2;
	DMACHANNELREGS	reserved1;
	volatile UNS_32   dma_global_int;
	volatile UNS_32   reserved2[15];
} DMACREGS;

/***********************************************************************
 * DMA Channel Control Register Bit Fields
 * DMA Channel Interrupt Register Bit Fields
 * DMA Channel Status Register Bit Fields
 **********************************************************************/ 
#define DMAC_STALL            _BIT(0)
#define DMAC_NFB              _BIT(1)
#define DMAC_CHERROR          _BIT(3)
#define DMAC_ENABLE           _BIT(4)
#define DMAC_ABORT            _BIT(5)
#define DMAC_ICE              _BIT(6)
#define DMAC_NEXTBUFFER       _BIT(6)
#define DMAC_CURRENTSTATE(n)  (((n)&0x30) >> 4)
#define DMAC_STATUS_BYTES(n)  (((n)&0xF80) >> 7)

/***********************************************************************
 * DMA Global Interrupt Register Bit Fields
 **********************************************************************/
#define DMAC_USBTXINT_BIT  (0)
#define DMAC_USBRXINT_BIT  (1)
#define DMAC_MMCTXINT_BIT  (2)
#define DMAC_MMCRXINT_BIT  (3)
#define DMAC_AACRX0INT_BIT (4)
#define DMAC_AACTX0INT_BIT (5)
#define DMAC_AACRX1INT_BIT (6)
#define DMAC_AACTX1INT_BIT (7)
#define DMAC_AACRX2INT_BIT (8)
#define DMAC_AACTX2INT_BIT (9)
  
#define DMAC_USBTXINT   _BIT(DMAC_USBTXINT_BIT)
#define DMAC_USBRXINT   _BIT(DMAC_USBRXINT_BIT)
#define DMAC_MMCTXINT   _BIT(DMAC_MMCTXINT_BIT)
#define DMAC_MMCRXINT   _BIT(DMAC_MMCRXINT_BIT)
#define DMAC_AACRX0INT  _BIT(DMAC_AACRX0INT_BIT)
#define DMAC_AACTX0INT  _BIT(DMAC_AACTX0INT_BIT)
#define DMAC_AACRX1INT  _BIT(DMAC_AACRX1INT_BIT)
#define DMAC_AACTX1INT  _BIT(DMAC_AACTX1INT_BIT)
#define DMAC_AACRX2INT  _BIT(DMAC_AACRX2INT_BIT)
#define DMAC_AACTX2INT  _BIT(DMAC_AACTX2INT_BIT)

#endif /* LH7A400_DMAC_H */