lh7a400_wdt.h

sharp触摸屏测试代码

/**********************************************************************
 *	$Workfile:   LH7A400_wdt.h  $
 *	$Revision:   1.4  $
 *	$Author:   SuryanG  $
 *	$Date:   Apr 23 2002 18:39:04  $
 *
 *	Project: LH7A400 headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for LH7A400 component:
 *      	Watchdog Timer
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *	$Log:   P:/PVCS6_6/archives/SOC/Processors/LH7A400/LH7A400_wdt.h-arc  $
 * 
 *    Rev 1.4   Apr 23 2002 18:39:04   SuryanG
 * Corrected WDT_CTRL_RSP_RESET and 
 * WDT_CTRL_RSP_FIQ defines.
 * 
 *    Rev 1.3   Apr 02 2002 12:10:46   SuryanG
 * Made structure definition comply with coding standards.
 * 
 *    Rev 1.2   Apr 02 2002 10:22:24   SuryanG
 * Added legal disclaimer. Converted to SMA types.
 * 
 *    Rev 1.1   Nov 08 2001 17:04:34   SuryanG
 * Corrected error in definition of WDT_CTRL_TOP (to WDT_CTRL_TOP(n))
 * 
 *    Rev 1.0   Sep 19 2001 17:23:50   BarnettH
 * Initial revision.
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_WDT_H
#define LH7A400_WDT_H

#include "SMA_types.h"

/*
 * Watchdog Timer Module Register Structure
 */ 
typedef struct 
{
   volatile UNS_32   wdctlr;  /* Control */ 
   volatile UNS_32   wdcntr;  /* Counter Reset */ 
   volatile UNS_32   wdtstr;  /* Test */ 
   volatile UNS_32   wdcnt0;  /* Counter Bits [7:0] */ 
   volatile UNS_32   wdcnt1;  /* Counter Bits [15:8] */ 
   volatile UNS_32   wdcnt2;  /* Counter Bits [23:16] */ 
   volatile UNS_32   wdcnt3;  /* Counter Bits [31:24] */ 
} WDTIMERREGS;

/**********************************************************************
 * Watchdog Timer Register Bit Fields
 *********************************************************************/ 

/**********************************************************************
 * Watchdog Control Register Bit Fields
 *********************************************************************/ 
#define  WDT_CTRL_DISABLE     0
#define  WDT_CTRL_ENABLE      _SBF(0,1)
#define  WDT_CTRL_RSP_RESET   _SBF(1,0)		
#define  WDT_CTRL_RSP_FIQ     _SBF(1,1)		
#define  WDT_CTRL_FRZ_ENABLE  _BIT(3)
#define  WDT_CTRL_TOP_WIDTH   4
#define  WDT_CTRL_TOP(n)      _SBF(4,((n)&_BITMASK(WDT_CTRL_TOP_WIDTH)))

/**********************************************************************
 * Watchdog Counter Reset Register Bit Fields
 *********************************************************************/ 
#define  WDT_WDCNTR        (0x1984)

/**********************************************************************
 * Watchdog Register Bit Fields
 *********************************************************************/ 
#define WDT_WD_NWDFIQ         _BIT(7)
#define WDT_WD_NWDRES         _BIT(6)
#define WDT_WD_RSP            _SBF(4,3)

#endif /* LH7A400_WDT_H */