lh7a400_sdramc.h

sharp触摸屏测试代码

/**********************************************************************
 *	$Workfile:   lh7a400_sdramc.h  $
 *	$Revision:   1.2  $
 *	$Author:   SuryanG  $
 *	$Date:   Apr 02 2002 12:12:14  $
 *
 *	Project: LH7A400 headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for the LH7A400 component:
 *      	SDRAM Controller
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *	$Log:   P:/PVCS6_6/archives/SOC/IP/LH7A400 IP/LH7A400/lh7a400_sdramc.h-arc  $
 * 
 *    Rev 1.2   Apr 02 2002 12:12:14   SuryanG
 * Made structure definition comply with coding standards.
 * 
 *    Rev 1.1   Apr 02 2002 10:01:54   SuryanG
 * Added legal disclaimer.
 * 
 *    Rev 1.0   Oct 04 2001 14:32:42   BarnettH
 * Initial revision.
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_SDRAMC_H
#define LH7A400_SDRAMC_H

#include "SMA_types.h"

/*
 * SDRAM Controller Module Register Structure
 */ 
typedef struct
{
   volatile UNS_32      reserved;
   volatile UNS_32      global;
   volatile UNS_32      refresh;
   volatile UNS_32      boot;
   volatile UNS_32      nsdcs0;
   volatile UNS_32      nsdcs1;
   volatile UNS_32      nsdcs2;
   volatile UNS_32      nsdcs3;
} SDRAMREGS;

/**********************************************************************
 * SDRAM Configuration Register Bit Fields
 *********************************************************************/ 
#define SDRAM_GLOBAL_CKE         _BIT(31)
#define SDRAM_GLOBAL_CLKSHUTDOWN _BIT(30)
#define SDRAM_GLOBAL_LCR         _BIT(6)
#define SDRAM_GLOBAL_SMEMBUSY    _BIT(5)
#define SDRAM_GLOBAL_MRS         _BIT(1)
#define SDRAM_GLOBAL_INITIALISE  _BIT(0)
#define SDRAM_GLOBAL_NOP         (_SBF(0,3)&0x43)
#define SDRAM_GLOBAL_PREALL      (_SBF(0,0x1)&0x43)
#define SDRAM_GLOBAL_ENAMODE     (_SBF(0,0x2)&0x43)
#define SDRAM_GLOBAL_ENACMD      (_SBF(0,0x42)&0x43)
#define SDRAM_GLOBAL_NORMAL      (_SBF(0,0)&0x43)

/**********************************************************************
 * SDRAM nSDCSx Device Configuration Register Bit Fields
 *********************************************************************/ 
#define SDRAM_NSDCS_AUTOPRECHARGE   _BIT(24)
#define SDRAM_NSDCS_RASTOCAS_RASL2  _SBF(20,0x2)
#define SDRAM_NSDCS_RASTOCAS_RASL3  _SBF(20,0x3)
#define SDRAM_NSDCS_WBL             _BIT(19)
#define SDRAM_NSDCS_CASLAT2         _SBF(16,0x01)
#define SDRAM_NSDCS_CASLAT3         _SBF(16,0x02)
#define SDRAM_NSDCS_CASLAT4         _SBF(16,0x03)
#define SDRAM_NSDCS_CASLAT5         _SBF(16,0x04)
#define SDRAM_NSDCS_CASLAT6         _SBF(16,0x05)
#define SDRAM_NSDCS_CASLAT7         _SBF(16,0x06)
#define SDRAM_NSDCS_CASLAT8         _SBF(16,0x07)
#define SDRAM_NSDCS_2KPAGE          _BIT(6)
#define SDRAM_NSDCS_SROMLL          _BIT(5)
#define SDRAM_NSDCS_SROM512         _BIT(4)
#define SDRAM_NSDCS_BANKCOUNT4      _BIT(3)
#define SDRAM_NSDCS_EBW32           0
#define SDRAM_NSDCS_EBW16           _BIT(2)

/**********************************************************************
 * SDRAM Boot Status Register Bit Fields
 *********************************************************************/ 
#define SDRAM_BOOT_MEDCHG_SYNCH     _BIT(2)
#define SDRAM_BOOT_MEDCHG_ASYNCH    0
#define SDRAM_BOOT_SYNCHROM32       _SBF(0,0x03)
#define SDRAM_BOOT_SYNCHFLASH32     _SBF(0,0x02)
#define SDRAM_BOOT_SYNCHROM16       _SBF(0,0x01)
#define SDRAM_BOOT_SYNCHFLASH16     _SBF(0,0x00)
#define SDRAM_BOOT_ASYNCH32         _SBF(0,0x02)
#define SDRAM_BOOT_ASYNCH16         _SBF(0,0x01)
#define SDRAM_BOOT_ASYNCH8          _SBF(0,0x00)
#define SDRAM_BOOT_ROM8             (SDRAM_BOOT_ASYNCH8 | \
                                       SDRAM_BOOT_ASYNCHROM)
#define SDRAM_BOOT_ROM16            (SDRAM_BOOT_ASYNCH16 | \
                                       SDRAM_BOOT_ASYNCHROM)
#define SDRAM_BOOT_ROM32            (SDRAM_BOOT_ASYNCH32 | \
                                       SDRAM_BOOT_ASYNCHROM)
#define SDRAM_BOOT_SFLASH16         (SDRAM_BOOT_SYNCHFLASH16 | \
                                       SDRAM_BOOT_SYNCHROM)
#define SDRAM_BOOT_SROM16           (SDRAM_BOOT_SYNCHROM16 | \
                                       SDRAM_BOOT_SYNCHROM)
#define SDRAM_BOOT_SFLASH32         (SDRAM_BOOT_SYNCHFLASH32 | \
                                       SDRAM_BOOT_SYNCHROM)
#define SDRAM_BOOT_SROM32           (SDRAM_BOOT_SYNCHROM32 | \
                                       SDRAM_BOOT_SYNCHROM)

/**********************************************************************
 * SDRAM Refresh Timer Register Bit Fields
 *********************************************************************/ 
#define SDRAM_REFTMR_REFCNT(n)      ((n)&0xFFFF)

#endif /* LH7A400_SDRAMC_H */