📄 lh7a400_csc_driver.c.bak
字号:
NOP
NOP
NOP
NOP
}
break;
case CLKSET_166_42_21:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_166_42_21;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_166_83_21:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_166_83_21;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_166_83_42:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_166_83_42;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_175_44_22:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_175_44_22;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_175_87_22:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_175_87_22;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_175_87_43:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_175_87_43;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_184_46_23:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_184_46_23;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_184_92_23:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_184_92_23;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_184_92_46:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_184_92_46;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_190_48_24:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_190_48_24;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_190_96_24:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_190_96_24;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_190_96_48:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_190_96_48;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_200_50_25:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_200_50_25;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_200_100_25:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_200_100_25;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_200_100_50:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_200_100_50;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
default:
#ifndef PROTO_LH7A400
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_ASYNCH
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
#endif
CLKSC->clkset = CLKSET_DEFAULT;
__asm
{
NOP
NOP
NOP
NOP
NOP
#ifdef PROTO_LH7A400
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
#endif
}
break;
}
}
/*********************************************************************
* Function: csc_get_cpuclk
* Purpose:
* Compute the current CPU value from the settings in the
* CLKSET register
*
* Processing:
* Extract the various variables from the CLKSET register and
use them in the equation described in the LH7A400
Programmers Manual to reverse compute the clock frequency.
*
* Parameters: None
* Outputs: None
* Returns: The current CPU frequency
*********************************************************************/
UNS_32 csc_get_cpuclk(void)
{
UNS_32 m1;
UNS_32 m2;
UNS_32 p;
UNS_32 ps;
register UNS_32 tmp;
tmp = CLKSC->clkset;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
m1 = (tmp >> 7) & 0x0F;
m2 = (tmp >> 11) & 0x1F;
p = (tmp >> 2) & 0x1F;
ps = (tmp >> 18) & 0x03;
return (((((m2 + 2) * LH7A400_BASE_CLOCK) >> ps) / (p + 2)) \
* (m1 + 2));
}
/**********************************************************************
*
* Function: UNS_32 LH7A400_get_hclk
*
* Author: KovitzP
*
* Purpose:
* To calculate and return the programmed value of HCLK
*
* Parameters:
* None
*
* Returns:
* Current programmed frequency of HCLK
*
* Notes:
* Useful for configuring the refresh rate of SDRAM, or LCD timing,
* ect...
*
**********************************************************************/
UNS_32 LH7A400_get_hclk(void)
{
UNS_32 m1;
UNS_32 m2;
UNS_32 p;
UNS_32 ps_pow;
UNS_32 hclkdiv;
UNS_32 gclk;
UNS_32 hclk;
/* compute hclk based on current system clock settings
see InfoStream Programming Manual page 12-13 */
m1 = (CLKSC->clkset >> 7) & 0xf;
m2 = (CLKSC->clkset >> 11) & 0x1f;
p = (CLKSC->clkset >> 2) & 0x1f;
ps_pow = 1 << ( (CLKSC->clkset >> 18) & 0x3);
hclkdiv = CLKSC->clkset & 0x3;
gclk = ((m1 + 2) * (m2 + 2) * (LH7A400_BASE_CLOCK / 100) / ((p+2)
* ps_pow))* 100 ;
hclk = gclk / (hclkdiv + 1);
return hclk;
}
/*********************************************************************
* Function: csc_get_pclk
* Purpose:
* Compute the current PCLK value from the settings in the
* CLKSET register
*
* Processing:
* Compute PCLK from the AHB clock and the APB divider.
*
* Parameters: None
* Outputs: None
* Returns: The current PCLK frequency
*********************************************************************/
UNS_32 csc_get_pclk(void)
{
register UNS_32 tmp;
UNS_32 pdiv;
tmp = CLKSC->clkset;
pdiv = 2 ^ ((tmp >> 16) & 0x3);
return (LH7A400_get_hclk () / pdiv);
}
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