📄 lh7a400_csc_driver.c.bak
字号:
/*********************************************************************
* Function: csc_no_apb_wait
* Purpose:
* Determine whether APB peripheral writes inserts wait states
* on the AHB
*
* Processing:
* Reads the APBWAIT register in the CSC
*
* Parameters: None
* Outputs: None
* Returns: 0 if the APB bridge inserts waits on APB writes
1 if the APB bridge does not insert waits on APB writes
*********************************************************************/
UNS_32 csc_no_apb_wait(void)
{
return(~(CLKSC->apbwait));
}
/*********************************************************************
* Function: csc_apb_wait
* Purpose:
* Control the APB wait state insertion
*
* Processing:
* Sets or resets the NO_WRITE_WAIT field in the APBWAIT
* register based on the argument passed
*
* Parameters: wait - 1 if no wait is desired
* 0 if it is desired that the APB bridge insert
* wait states on the AHB for (peripheral writes
* Outputs: None
* Returns: Nothing
*********************************************************************/
void csc_apb_wait(UNS_32 wait)
{
if (wait)
{
CLKSC->apbwait = 0;
}
else
{
CLKSC->apbwait = APB_NO_WRITE_WAIT;
}
}
/**********************************************************************
*
* Function: void LH7A400_clock_set (UNS_32 clkset_register_setting)
*
* Author: barnetth
*
* Purpose:
* To set the RCPC Prescale registers in the proper order
*
* Processing:
* For the desired clock setting, set the CpuClkPrescale and
* then set the HCLKClkPrescale.
*
* Parameters:
* UNS_32 clkset_register_setting - A value selected from the
* following constants:
*
* CLKSET_33_33_8
* CLKSET_33_33_16
* CLKSET_50_50_12
* CLKSET_50_50_25
* CLKSET_66_33_8
* CLKSET_66_33_16
* CLKSET_66_66_16
* CLKSET_66_66_33
* CLKSET_75_75_19
* CLKSET_75_75_37
* CLKSET_100_50_12
* CLKSET_100_50_25
* CLKSET_100_100_12
* CLKSET_100_100_50
* CLKSET_132_33_8
* CLKSET_132_33_16
* CLKSET_132_66_16
* CLKSET_132_66_33
* CLKSET_150_75_19
* CLKSET_150_75_37
* CLKSET_166_42_21
* CLKSET_166_83_21
* CLKSET_166_83_42
* CLKSET_175_44_22
* CLKSET_175_87_43
* CLKSET_184_46_23
* CLKSET_190_48_24
* CLKSET_200_50_25
* CLKSET_200_100_25
* CLKSET_200_100_50
*
* See LH7A400_evb.h
*
* Outputs: None
*
* Returns: None
*
* Notes:
* (1) DEFAULT is to set the core to 200 MHz, the AHB to 50 MHz
*
**********************************************************************/
void LH7A400_clock_set (UNS_32 clkset_register_setting)
{
switch (clkset_register_setting)
{
case CLKSET_33_33_8:
CLKSC->clkset = CLKSET_33_33_8;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC p15, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_33_33_16:
CLKSC->clkset = CLKSET_33_33_16;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_50_50_12:
CLKSC->clkset = CLKSET_50_50_12;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_50_50_25:
CLKSC->clkset = CLKSET_50_50_25;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_66_33_8:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_66_33_8;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_66_33_16:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_66_33_16;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_66_66_16:
CLKSC->clkset = CLKSET_66_66_16;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_66_66_33:
CLKSC->clkset = CLKSET_66_66_33;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_75_75_19:
CLKSC->clkset = CLKSET_75_75_19;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_75_75_37:
CLKSC->clkset = CLKSET_75_75_37;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_100_50_12:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_100_50_12;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_100_50_25:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_100_50_25;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_100_100_12:
CLKSC->clkset = CLKSET_100_100_12;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_100_100_50:
CLKSC->clkset = CLKSET_100_100_50;
__asm
{
NOP
NOP
NOP
NOP
NOP
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
AND r1, r1, #(_BITMASK(30))
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
break;
case CLKSET_132_33_8:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_132_33_8;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_132_33_16:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_132_33_16;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_132_66_16:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_132_66_16;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_132_66_33:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_132_66_33;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_150_75_19:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_150_75_19;
__asm
{
NOP
NOP
NOP
NOP
NOP
}
break;
case CLKSET_150_75_37:
__asm
{
MRC MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
MOV r2, MMU_CONTROL_NF
AND r1, r1, #(_BITMASK(30))
ORR r1, r1, r2
MCR MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
}
CLKSC->clkset = CLKSET_150_75_37;
__asm
{
NOP
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -