lh7a400_aac.h

sharp触摸屏测试代码

/**********************************************************************
 *	$Workfile:   LH7A400_aac.h  $
 *	$Revision:   1.3  $
 *	$Author:   SuryanG  $
 *	$Date:   Apr 02 2002 12:14:02  $
 *
 *	Project: LH7A400 headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for the LH7A400 component:
 *      	Advanced Audio Codec Controller
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *	$Log:   P:/PVCS6_6/archives/SOC/LH7A400/Processor/LH7A400_aac.h-arc  $
 * 
 *    Rev 1.3   Apr 02 2002 12:14:02   SuryanG
 * Made structure definition comply with coding standards.
 * 
 *    Rev 1.2   Apr 01 2002 10:42:14   SuryanG
 * Updated structure names to comply with standard. Added legal 
 * disclaimer.
 * 
 *    Rev 1.1   Feb 06 2002 17:43:32   BarnettH
 * Got rid of PACKED pre-define
 * 
 *    Rev 1.0   Jan 11 2002 17:20:36   SuryanG
 * Initial revision.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *  
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#if !defined (LH7A400_AAC_H)
#define LH7A400_AAC_H

#include "SMA_types.h"

/***********************************************************************
 * AAC Module Register Structures
 **********************************************************************/ 
typedef struct
{
    volatile UNS_32     dr;   /* data register */
    volatile UNS_32     rxcr; /* receive control register */
    volatile UNS_32     txcr; /* transmit control register */
    volatile UNS_32     sr;   /* status register */
    volatile UNS_32     risr; /* raw interrupt status register 
                                (read only) */
    volatile UNS_32     isr;  /* interrupt status register 
                                (read only) */
    volatile UNS_32     ie;   /* interrupt enable register */
    volatile UNS_32     reserved;
} AAC_FIFO_REGS_T;

typedef struct
{
    AAC_FIFO_REGS_T     fifo[4];      /* FIFO register set */
    volatile UNS_32     s1data;     /* data received/transmitted 
                                       on SLOT1 */
    volatile UNS_32     s2data;     /* data received/transmitted 
                                       on SLOT2 */
    volatile UNS_32     s12data;    /* data received/transmitted 
                                       on SLOT12 */
    volatile UNS_32     rgis;       /* raw global interrupt status */
    volatile UNS_32     gis;        /* global interrupt status */
    volatile UNS_32     im;         /* interrupt mask register */
    volatile UNS_32     eoi;        /* end-of-interrupt register */
    volatile UNS_32     gcr;        /* global control register */
    volatile UNS_32     reset;      /* AAC reset control register */
    volatile UNS_32     sync;       /* AAC sync control register */
    volatile UNS_32     gcis;       /* global channel FIFO interrupt
                                       status register */
 } AACREGS;

/***********************************************************************
 * AAC FIFO Channel Control Registers Bit Field Definitions
 **********************************************************************/ 
/***********************************************************************
 * AAC FIFO Data Register Bit Fields
 **********************************************************************/ 
#define DR_DATA_WIDTH       (20)
#define DR_DATA(n)          (_BITMASK(DR_DATA_WIDTH) & (n))

/***********************************************************************
 * AAC FIFO Receive Control Register Bit Fields
 **********************************************************************/ 
#define RXCR_REN            _BIT(0)
#define RXCR_RX(n)          _BIT(n)
#define RXCR_RSIZE_WIDTH    (2)
#define RXCR_RSIZE(n)       _SBF(13, _BITMASK(RXCR_RSIZE_WIDTH) & (n))
#define RXCR_CM             _BIT(15)
#define RXCR_FDIS           _BIT(16)
#define RXCR_TOC_WIDTH      (12)
#define RXCR_TOC(n)         _SBF(17, _BITMASK(RXCR_TOC_WIDTH) & (n))

/***********************************************************************
 * AAC FIFO Transmit Control Register Bit Fields
 **********************************************************************/ 
#define TXCR_TEN           _BIT(0)
#define TXCR_TX(n)         _BIT(n)
#define TXCR_TSIZE_WIDTH   (2)
#define TXCR_TSIZE(n)      _SBF(13, _BITMASK(TXCR_TSIZE_WIDTH) & (n))
#define TXCR_CM            _BIT(15)
#define TXCR_FDIS          _BIT(16)

/***********************************************************************
 * AAC FIFO Status Register Bit Fields
 **********************************************************************/ 
#define SR_RXFE            _BIT(0)
#define SR_TXFE            _BIT(1)
#define SR_RXFF            _BIT(2)
#define SR_TXFF            _BIT(3)
#define SR_TXBUSY          _BIT(4)
#define SR_RXOE            _BIT(5)
#define SR_TXUE            _BIT(6)

/***********************************************************************
 * AAC FIFO Raw Interrupt Status Register Bit Fields
 **********************************************************************/ 
#define RISR_TCIS          _BIT(0)
#define RISR_RCIS          _BIT(1)
#define RISR_TIS           _BIT(2)
#define RISR_RIS           _BIT(3)

/***********************************************************************
 * AAC FIFO Interrupt Status Register Bit Fields
 **********************************************************************/ 
#define ISR_TCIS           _BIT(0)
#define ISR_RCIS           _BIT(1)
#define ISR_TIS            _BIT(2)
#define ISR_RIS            _BIT(3)

/***********************************************************************
 * AAC FIFO Interrupt Enable Register Bit Fields
 **********************************************************************/ 
#define RISR_TCIE          _BIT(0)
#define RISR_RCIE          _BIT(1)
#define RISR_TIE           _BIT(2)
#define RISR_RIE           _BIT(3)

/***********************************************************************
 * AAC Slot1 data Register Bit Fields
 **********************************************************************/ 
#define S1DATA_MASK_WIDTH  (7)
#define S1DATA_MASK        _SBF(0, _BITMASK(S1DATA_MASK_WIDTH))

/***********************************************************************
 * AAC Slot2 data Register Bit Fields
 **********************************************************************/ 
#define S2DATA_MASK_WIDTH  (16)
#define S2DATA_MASK        _SBF(0, _BITMASK(S2DATA_MASK_WIDTH))

/***********************************************************************
 * AAC Slot12 data Register Bit Fields
 **********************************************************************/ 
#define S12DATA_MASK_WIDTH (20)
#define S12DATA_MASK       _SBF(0, _BITMASK(S12DATA_MASK_WIDTH))

/***********************************************************************
 * AAC Raw Global Interrupt Status Register Bit Fields
 **********************************************************************/ 
#define RGIS_SLOT1TXCOMPLETE	   _BIT(0)
#define RGIS_SLOT2RXVALID   	   _BIT(1)
#define RGIS_GPIOTXCOMPLETE 	   _BIT(2)
#define RGIS_GPIOINTRX      	   _BIT(3)
#define RGIS_RWIS           	   _BIT(4)
#define RGIS_CODECREADY     	   _BIT(5)

/***********************************************************************
 * AAC Global Interrupt Status Register Bit Fields
 **********************************************************************/ 
#define GIS_SLOT1TXBUSY          _BIT(0)
#define GIS_SLOT2RXVALID         _BIT(1)
#define GIS_GPIOBIS              _BIT(2)
#define GIS_GPIOIS               _BIT(3)
#define GIS_WIS                  _BIT(4)
#define GIS_CODECREADY           _BIT(5)

/***********************************************************************
 * AAC Global Interrupt Enable Register Bit Fields
 **********************************************************************/ 
#define IE_SLOT1TXBUSY          _BIT(0)
#define IE_SLOT2RXVALID         _BIT(1)
#define IE_GPIOBIE              _BIT(2)
#define IE_GPIOIE               _BIT(3)
#define IE_WIE                  _BIT(4)
#define IE_CODECREADY           _BIT(5)

/***********************************************************************
 * AAC End of Interrupt Register Bit Fields
 **********************************************************************/ 
#define EOI_WISC                _BIT(0)
#define EOI_CODECREADY          _BIT(1)

/***********************************************************************
 * AAC Global Control Register Bit Fields
 **********************************************************************/ 
#define GCR_AACIFE              _BIT(0)
#define GCR_LOOP                _BIT(1)
#define GCR_OCR                 _BIT(2) /* Override Codec Ready */

/***********************************************************************
 * AAC Reset Register Bit Fields
 **********************************************************************/ 
#define RESET_TIMEDRESET        _BIT(0)
#define RESET_FORCEDRESET       _BIT(1)
#define RESET_EFORCER           _BIT(2)

/***********************************************************************
 * AAC Sync Port Control Register Bit Fields
 **********************************************************************/ 
#define SYNC_TIMEDSYNC          _BIT(0)
#define SYNC_FORCEDSYNC         _BIT(1)
#define SYNC_EFORCES            _BIT(2)

/***********************************************************************
 * AAC Global Channel FIFO Interrupt Status Register Bit Fields
 **********************************************************************/ 
#define GCIS_AACISR1_WIDTH      (4)
#define GCIS_AACISR1            _SBF(0, _BITMASK(GCIS_AACISR1_WIDTH))
#define GCIS_AACISR2_WIDTH      (4)
#define GCIS_AACISR2            _SBF(4, _BITMASK(GCIS_AACISR2_WIDTH))
#define GCIS_AACISR3_WIDTH      (4)
#define GCIS_AACISR3            _SBF(8, _BITMASK(GCIS_AACISR3_WIDTH))
#define GCIS_AACISR4_WIDTH      (4)
#define GCIS_AACISR4            _SBF(12, _BITMASK(GCIS_AACISR4_WIDTH))
#define GCIS_AACGIS_WIDTH       (6)
#define GCIS_AACGIS             _SBF(16, _BITMASK(GCIS_AACGIS_WIDTH))


#endif /* LH7A400_AAC_H */