lh7a400_evbmeminit.c

sharp触摸屏测试代码

 ******  The Micron SDRAM parts will work fine with the JEDEC sequence,
 *  but also allow for a quicker init sequence of:
 *
 *  APPLY POWER (Vdd/Vddq equally, and CLK is stable)
 *  Wait at least 100uS (during which time start applying and
 *     continue applying NOP or COMMAND INHIBIT)
 *  PRECHARGE all
 *  2 AUTO REFRESH COMMANDS (min requirement, more than 2 is also ok)
 *  LOAD MODE REGISTER
 *  SDRAM is ready for operation
 *
 *  Notes:  The order of the AUTO REFRESH commands and LOAD MODE
 *          REGISTER can be reversed if preferred.
 *          User should stop watchdog timer and disable caches and MMU's
 *          before calling this function.
 *
 **********************************************************************/


void LH7A400_init_sdram (void)
{
    volatile UNS_32 tmp;
    UNS_32 current_HCLK;

    current_HCLK = csc_get_hclk();
    LH7A400_mem_timer (100);

    /* configure "device config register" nSDCE0-1 for proper width */
    /* SDRAM->nsdcs0 = 0x00210008; */   /* SDRAM */
    SDRAM->nsdcs0 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                     SDRAM_NSDCS_CASLAT2 |
					 //SDRAM_NSDCS_WBL |
                     SDRAM_NSDCS_BANKCOUNT4 |
#if defined (MMU_MAP_SDRAM_0_SROMLL)
                     SDRAM_NSDCS_SROMLL |       
#endif
                     SDRAM_NSDCS_EBW32);

    //SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
    //                 SDRAM_NSDCS_CASLAT2 |
  //                   SDRAM_NSDCS_BANKCOUNT4 |
//#if defined (MMU_MAP_SDRAM_0_SROMLL)
//                     SDRAM_NSDCS_SROMLL |       
//#endif
//                     SDRAM_NSDCS_EBW16);

    /* configure "device config register" nSDCE3 for proper width */
    /* SDRAM->nsdcs3 = 0x012a000c;       SyncFlash */
/*
    if (current_HCLK <= 66000000)
    {
        SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                         SDRAM_NSDCS_CASLAT2 |
                         SDRAM_NSDCS_BANKCOUNT4 |
                         SDRAM_NSDCS_EBW16);
    }
    else
    {
        SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                         SDRAM_NSDCS_CASLAT3 |
                         SDRAM_NSDCS_BANKCOUNT4 |
                         SDRAM_NSDCS_EBW16);
    }
*/
    LH7A400_mem_timer (100);

    /* issue continuous NOP commands (INIT & MRS set) */
    /* SDRAM->global = 0x80000003; */
    SDRAM->global = (UNS_32)(SDRAM_GLOBAL_CKE | SDRAM_GLOBAL_NOP);

    /*         DELAY   */
    /* load ~200us value to timer1 */
    LH7A400_mem_timer (200);

    /* issue a "pre-charge all" command */
    /* SDRAM->global = 0x80000001; */
    SDRAM->global = (UNS_32)(SDRAM_GLOBAL_CKE | SDRAM_GLOBAL_PREALL);

    /* Minimum refresh pulse interval (tRFC) for MT48LCM16A2-75=64nsec,
     * 100nsec provides more than adequate interval. Only need 2 refresh
     * clks, so 10 is more than adequate.
     * ((1/100nsec) * 10 clks) / HCLK = usec delay value
     */
    SDRAM->refresh = SDRAM_REFTMR_REFCNT(100000000 / current_HCLK);

    /* DELAY   */
    /* load ~250us value to timer1 */
    LH7A400_mem_timer (5);

    /* Recommended refresh interval for normal operation of the Micron
     * MT48LCM16A2-75 = 15.625usec (64KHz rate).
     * ((HCLK / 64000) - 1) = refresh counter interval rate, (subtract 
     * one for safety margin).
     */
    SDRAM->refresh = SDRAM_REFTMR_REFCNT((current_HCLK / 64000) - 1);

    /* select mode register update mode */
    /* SDRAM->global = 0x80000002; */
    SDRAM->global = (UNS_32)(SDRAM_GLOBAL_CKE | SDRAM_GLOBAL_ENAMODE);

    /* Program the SDRAM internal mode registers on bank nSDCE0, 1, & 3
     * and reconfigure the SDRAM chips.  Bus speeds up to 100MHz
     * requires use of a CAS latency = 2.
     * To get correct value on address bus CAS cycle, requires a shift
     * by 10 for 32bit mode, shift by 9 for 16bit mode
     */
    tmp = *((UNS_32 *)(SDRAM_SDCE0_BASE | _SBF(10, 0x22)));
//    tmp = *((UNS_32 *)(SDRAM_SDCE3_BASE | _SBF(9, 0x23)));

/*    SDRAM->nsdcs0 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                     SDRAM_NSDCS_CASLAT2 |
					 //SDRAM_NSDCS_WBL |
                     SDRAM_NSDCS_BANKCOUNT4 |
#if defined (MMU_MAP_SDRAM_0_SROMLL)
                     SDRAM_NSDCS_SROMLL |       
#endif
                     SDRAM_NSDCS_EBW32);
*/
//    SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
//                     SDRAM_NSDCS_CASLAT2 |
//                     SDRAM_NSDCS_BANKCOUNT4 |
//#if defined (MMU_MAP_SDRAM_0_SROMLL)
//                     SDRAM_NSDCS_SROMLL |       
//#endif
//                     SDRAM_NSDCS_EBW16);


    if (current_HCLK <= 66000000)
    {
        tmp = *((UNS_32 *)(SDRAM_SDCE3_BASE | _SBF(9, 0x223)));
        SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                         SDRAM_NSDCS_CASLAT2 |
                         SDRAM_NSDCS_BANKCOUNT4 |
                         SDRAM_NSDCS_EBW16);
    }
    else
    {
        tmp = *((UNS_32 *)(SDRAM_SDCE3_BASE | _SBF(9, 0x233)));
        SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                         SDRAM_NSDCS_CASLAT3 |
                         SDRAM_NSDCS_BANKCOUNT4 |
                         SDRAM_NSDCS_EBW16);
    }

    /* select normal operating mode */
    /* SDRAM->global = 0x80000000; */
    SDRAM->global = (UNS_32)(SDRAM_GLOBAL_CKE | SDRAM_GLOBAL_NORMAL);
}

/**********************************************************************
 * Function: LH7A400_reconfig_SDRAM
 *
 * Purpose: To reconfigure LH7A400 EVB implementation specific SDRAM
 *
 * Parameters: None
 *
 * Outputs: None
 *
 * Returns: None
 *
 * Notes: Function changes SDRAM wait state and refresh settings based
 *        on the current setting of HCLK
 *
 **********************************************************************/

void LH7A400_reconfig_SDRAM(void)
{
    volatile UNS_32 tmp;
    UNS_32 current_HCLK;

    current_HCLK = csc_get_hclk();

    /* Recommended refresh interval for normal operation of the Micron
     * MT48LCM16A2-75 = 15.625usec (64KHz rate).
     * ((HCLK / 64000) - 1) = refresh counter interval rate, (subtract 
     * one for safety margin).
     */
    SDRAM->refresh = SDRAM_REFTMR_REFCNT((current_HCLK / 64000) - 1);

    while (SDRAM->global & SDRAM_GLOBAL_SMEMBUSY)
        ;

    /* select mode register update mode */
    /* SDRAM->global = 0x80000002; */
    SDRAM->global = (UNS_32)(SDRAM_GLOBAL_CKE | SDRAM_GLOBAL_ENAMODE);

    /* 
     * Program the SDRAM internal mode registers on bank nSDCE0-1
     * and reconfigure the SDRAM chips.
     */
    SDRAM->nsdcs0 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                     SDRAM_NSDCS_CASLAT2 |
                     SDRAM_NSDCS_BANKCOUNT4 |
#if defined (MMU_MAP_SDRAM_0_SROMLL)
                     SDRAM_NSDCS_SROMLL |       
#endif
                     SDRAM_NSDCS_EBW32);

    SDRAM->nsdcs1 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                     SDRAM_NSDCS_CASLAT2 |
                     SDRAM_NSDCS_BANKCOUNT4 |
#if defined (MMU_MAP_SDRAM_0_SROMLL)
                     SDRAM_NSDCS_SROMLL |       
#endif
                     SDRAM_NSDCS_EBW32);

    tmp = *((UNS_32 *)(SDRAM_SDCE0_BASE | _SBF(10, 0x22)));

    tmp = *((UNS_32 *)(SDRAM_SDCE1_BASE | _SBF(10, 0x22)));

    /* SDRAM->nsdcs3 = 0x012a000c;       SyncFlash */
    if (current_HCLK <= 66000000) {
       tmp = *((UNS_32 *)(SDRAM_SDCE3_BASE | _SBF(9, 0x223)));
       SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                        SDRAM_NSDCS_CASLAT2 |
                        SDRAM_NSDCS_BANKCOUNT4 |
                        SDRAM_NSDCS_EBW16);
    } else {
       tmp = *((UNS_32 *)(SDRAM_SDCE3_BASE | _SBF(9, 0x233)));
       SDRAM->nsdcs3 = (SDRAM_NSDCS_RASTOCAS_RASL2 |
                        SDRAM_NSDCS_CASLAT3 |
                        SDRAM_NSDCS_BANKCOUNT4 |
                        SDRAM_NSDCS_EBW16);
    }

    SDRAM->global = (UNS_32)(SDRAM_GLOBAL_CKE | SDRAM_GLOBAL_NORMAL);

    while (SDRAM->global & SDRAM_GLOBAL_SMEMBUSY)
        ;
}

/**********************************************************************
 * Function: LH7A400_mem_timer
 *
 * Purpose: Specialized timer for limited periods used by SDRAM
 *          initialization delays.
 *
 * Parameters: time_val: approximate microseconds of delay wanted
 *
 * Outputs: None
 *
 * Returns: None
 *
 * Notes:
 *
 *********************************************************************/

static void LH7A400_mem_timer (UNS_32 time_val)
{
    /* At 508 KHz, ~2 microseconds per count
     * so halve the time_val in microseconds to yield counts
     */
    TIMER1->load = (time_val >> 1);
    /* enable free running timer1 508KHz */
    TIMER1->control = TIMER_CTRL_ENABLE | TIMER_CTRL_FREERUN |
                            TIMER_CTRL_508K;
    /* delay until timer is finished */
    /* check > 32767) indicating rollover */
    while(!(TIMER1->value & _BIT(15)))
        ;
    /* disable timer1  */
    TIMER1->control = TIMER_CTRL_DISABLE;
}