lh7a400_evbmeminit.c

sharp触摸屏测试代码

/**********************************************************************
 * $Workfile:   LH7A400_evbmeminit.c  $
 * $Revision:   1.0  $
 * $Author:   WellsK  $
 * $Date:   Sep 23 2002 13:52:02  $
 *
 * Project: LH7A400 CPU EVB
 *
 * Description:
 *    Memory Initialization routines.  Currently this file only
 *    initializes Bank Configuration registers for chip selects 0-3
 *    as they are defined in LH7A400_evb.h, SDRAM at 0xC0000000 &
 *    0xD0000000, and SyncFlash at 0xF0000000.
 *
 * Local Includes:
 *    LH7A400_evb.h
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_evbmeminit.c-arc  $
 * 
 *    Rev 1.0   Sep 23 2002 13:52:02   WellsK
 * Initial revision.
 * 
 *    Rev 1.0   Sep 14 2002 11:38:06   WellsK
 * Initial revision.
 * 
 *    Rev 1.10   Jul 02 2002 11:41:06   MaysR
 * Corrected error in refresh timer register value calculation.
 * 
 *    Rev 1.9   Jun 20 2002 16:50:46   MaysR
 * Added include for Clock and State Controller header file.
 * 
 *    Rev 1.8   Jun 13 2002 19:17:46   BarnettH
 * Eliminated "CLKIDX" references.  Changed to CLKSET scheme to 
 * eliminate necessity to maintain coherency across clock codes and 
 * assembly and C language files.
 * Removed superfluous code.
 * Cleaned up formatting.
 * 
 *    Rev 1.7   Apr 11 2002 17:07:14   BarnettH
 * Changed all function names to standard
 * Removed tabs
 * Formatted to standard.
 * 
 *    Rev 1.6   Nov 26 2001 11:12:34   MaysR
 * Added missing function headers.  Inserted missing comment for 
 * version 1.2.  Changed SDRAM and SyncFlash init lines to call _SBF.
 *
 *    Rev 1.5   Nov 15 2001 11:44:16   MaysR
 * Corrected incorrect SyncFlash CAS setting.
 *
 *    Rev 1.4   Nov 14 2001 19:00:46   MaysR
 * Added SyncFlash init code from Paul.  Removed SDRAM init code for 
 * speeds greater than 100MHz.
 *
 *    Rev 1.3   Nov 14 2001 16:09:20   MaysR
 * Corrected the SDRAM initialization routines for correct configuration
 * of SDRAM.
 * Added new routine to re-configure SDRAM for system speed changes.
 *
 *    Rev 1.2   Oct 18 2001 18:57:54   BarnettH
 * Corrected error in sdram_init for nSDCS1 (was nSDCS0)
 *
 *    Rev 1.1   Sep 28 2001 16:26:32   BarnettH
 * Move clock setup by a call from assembly language
 * Replaced "magic numbers" with manifest constants
 * Added clock speeds up to 200_100_50
 *
 *    Rev 1.0   Sep 18 2001 18:05:40   BarnettH
 * Initial revision.
 *
 ***********************************************************************
 * 
 *  Copyright (c) 2002 Sharp Microelectronics of the Americas
 *
 *  All rights reserved
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *********************************************************************/

#include "LH7A400_evb.h"
#include "LH7A400_evbutil.h"
#include "LH7A400_csc_driver.h"

static void LH7A400_init_smc (void);
static void LH7A400_mem_timer (UNS_32 delay);
void LH7A400_init_mem (void);
void LH7A400_init_sdram (void);
void LH7A400_reconfig_SDRAM (void);

/********************************************************************
 *
 * Funtion: LH7A400_init_mem (void)
 *
 * Purpose: Initialize configurations for external SRAM and SDRAM
 *
 * Parameters: None
 *
 * Outputs: None
 *
 * Returns: None.
 *
 * Notes: Short funtion that calls two other routines to configure
 *       memory.  If more init routines are added (i.e. for PC-CARD)
 *       they can be called from here.
 *       User should stop watchdog timer, and disable caches and MMU's
 *       before calling this function.
 *
 *******************************************************************/

void LH7A400_init_mem (void)
{
   /* init Static RAM */
   LH7A400_init_smc ();

   /* init Synchronous DRAM */
   LH7A400_init_sdram ();
}

/********************************************************************
 *
 * Funtion: LH7A400_init_smc (void)
 *
 * Purpose: Initialize Bank Configuration registers with parameters
 *          from LH7A400_evb.h
 *
 * Parameters: None.
 *
 * Outputs: None
 *
 * Returns: None.
 *
 * Notes: Programs bank configuration registers for chips selects 0-3.
 *
 *******************************************************************/

static void LH7A400_init_smc (void)
{
    /* nCS0 0x00000000 */
 //   SMC->bcr0 = (SMC_BCR_MW32 | SMC_BCR_WST2(31) | \
                        SMC_BCR_WST1(31));

    /* nCS1 0x10000000 */
    //SMC->bcr1 = SMC_BCR0_INIT;
	SMC->bcr1 = (SMC_BCR_MW16 | SMC_BCR_WST2(31) | \
                        SMC_BCR_WST1(31));


    /* CPLD */
    /* nCS2 0x20000000 */
    SMC->bcr2 = (SMC_BCR_MW16 | SMC_BCR_WST2(4) | \
                        SMC_BCR_WST1(31));
	//SMC->bcr2 = (SMC_BCR_MW16 | SMC_BCR_WST2(31) | SMC_BCR_WST1(31) | SMC_BCR_IDCY(15));

    /* nCS3 0x30000000 */
    SMC->bcr3 = SMC_BCR3_INIT;
}

/**********************************************************************
 * Function: LH7A400_init_sdram (void)
 *
 * Purpose: To initialize LH7A400 EVB implementation specific SDRAM
 *
 * Description: Function to initialize SDRAM
 *   Two external banks comprising two 8Mbit x 16 SDRAM chips per bank
 *   32 MBytes per bank, 64 MBytes total.
 *   Micron 128Mb MT48LC8M16A2TG-7EL
 *
 * nSDCE0 - 32MB at 0xC0000000 (SDRAM Bank0 Base)
 * nSDCE1 - 32MB at 0xD0000000 (SDRAM Bank1 Base)
 * nSDCE3 -  8MB at 0xF0000000 (SyncFlash Base)
 *
 *  Typical SDRAM controller sequence from SDRAMC TRM (PL170 DDI0159C):
 *
 *  1. Wait 100ms to allow SDRAMs power and clocks to
 *  stabilize.
 *
 *  2. Set the I and M bits. This automatically issues a
 *  NOP to the SDRAMs.
 *
 *  3. Wait 200ms.
 *
 * 4. Reset the M bit (I = 1, M = 0). This automatically
 *  issues a PRE-ALL to the SDRAMs.
 *
 *  5. Write 10 into the refresh timer register. This provides
 *  a refresh cycle every 10 clock cycles.
 *
 *  6. Wait for a time period equivalent to 80 clock cycles
 *  (8 refresh cycles).
 *
 *  7. Program the operational value into the refresh timer.
 *
 * 8. Select command write mode (I = 0, M = 1) and perform a
 *  read from each SDRAM connected to the controller. Address
 *  lines HADDR[26:11] encode the value output on the SDRAM
 *  address lines AddrOut[14:0]. See the SDRAM data sheet
 *  for the bit pattern programmed onto AddrOut[14:0],
 *  for the required operational mode.
 *
 *  9. Program configuration registers.
 *
 *  Note: Parameters programmed into the SDRAMs, such as
 *  burst length, RAS and CAS delays, must be consistent with
 *  the values written to configuration registers.  For X=0
 *  (x32 data path), use incremental burst length 4. For X=1
 *  (x16 data path), use incremental burst length 8.
 *
 *  10. Clear the M and I bits and set the other bits in
 *  configuration register 1 to their normal operational
 *  values.
 *
 *  11. The SDRAM is now ready for normal operation.
 *
 *
 *  ***** Micron Initialization Sequence from their data sheet
 *        for the Micron MC48LC8M16A2TG 8Mb x 16 SDRAM chip:
 *
 *  Initialization
 *
 *  SDRAMs must be powered up and initialized in a
 *  predefined manner. Operational procedures other than
 *  those specified may result in undefined operation. Once
 *  power is applied to VDD and VDDQ (simultaneously) and
 *  the clock is stable (stable clock is defined as a signal
 *  cycling within timing constraints specified for the clock
 *  pin), the SDRAM requires a 100祍 delay prior to issuing
 *  any command other than a COMMAND INHIBIT or NOP.
 *
 *  Starting at some point during this 100祍 period and
 *  continuing at least through the end of this period,
 *  COMMAND INHIBIT or NOP commands should be applied.
 *  Once the 100祍 delay has been satisfied with at least
 *  one COMMAND INHIBIT or NOP command having been applied,
 *  a PRECHARGE command should be applied. All banks must
 *  then be precharged, thereby placing the device in the
 *  all banks idle state.
 *
 *  Once in the idle state, two AUTO REFRESH cycles
 *  must be performed. After the AUTO REFRESH cycles are
 *  complete, the SDRAM is ready for mode register programming.
 *
 *  Because the mode register will power up in an
 *  unknown state, it should be loaded prior to applying any
 *  operational command.
 *
 ******  The JEDEC recommendation for initializing SDRAM is:
 *
 *  APPLY POWER (Vdd/Vddq equally, and CLK is stable)
 *  Wait 200uS
 *  PRECHARGE all
 *  8 AUTO REFRESH COMMANDS
 *  LOAD MODE REGISTER
 *  SDRAM is ready for operation
 *