lh7a400_ssp.h

sharp flash blob 的烧写代码

/**********************************************************************
 * $Workfile:   lh7a400_ssp.h  $
 * $Revision:   1.2  $
 * $Author:   SuryanG  $
 * $Date:   Apr 02 2002 10:07:58  $
 *
 * Project: LH7A400 headers
 *
 * Description:
 *   This file contains the structure definitions and manifest
 *   constants for the LH7A400 component:
 *     Synchronous Serial Port
 *
 * References:
 *   (1) Sharp LH7A400 Universal SoC User's Guide
 *
 * Revision History:
 * $Log:   P:/PVCS6_6/archives/SOC/IP/LH7A400 IP/LH7A400/lh7a400_ssp.h-arc  $
 * 
 *    Rev 1.2   Apr 02 2002 10:07:58   SuryanG
 * Added legal disclaimer.
 * 
 *    Rev 1.1   Jan 03 2002 17:58:02   KovitzP
 * got rid of PACKED and tab characters
 * 
 * Rev 1.0   Oct 04 2001 14:32:42   BarnettH
 * Initial revision.
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *      CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_SSP_H
#define LH7A400_SSP_H

#include "SMA_types.h"

/**********************************************************************
 * Synchronous Serial Port Register Structure
 *********************************************************************/ 
typedef struct 
{
   volatile UNS_32      cr0;
   volatile UNS_32      cr1;
   union 
   {
      volatile UNS_32      iir;
      volatile UNS_32      icr;
   } u;
   volatile UNS_32      dr;
   volatile UNS_32      cpsr;
   volatile UNS_32      sr;
} SSPREGS;

/**********************************************************************
 * Synchronous Serial Port Register Bit Fields
 *********************************************************************/ 

/**********************************************************************
 * SSP Control 0 Register Bit Fields
 *********************************************************************/ 
/* Valid range for argument to SSP_CR0_DSS(n) is [4-16] */ 
#define SSP_CR0_DSS(n)   _SBF(0,(((n)-1)&0x0F))   /* Data Size Select */ 
#define SSP_CR0_FRF_MOT   _SBF(4,0)   /* Motorola SPI frame */ 
#define SSP_CR0_FRF_TI   _SBF(4,1)   /* TI synchronous serial frame */ 
#define SSP_CR0_FRF_NS   _SBF(4,2)   /* National Microwire frame */ 
#define SSP_CR0_SSE      _BIT(7)      /* SSP Enable */ 
#define SSP_CR0_SCR(n)   _SBF(8,((n)&0xFF))   /* Serial Clock Rate */ 

/**********************************************************************
 * SSP Control 1 Register Bit Fields
 *********************************************************************/ 
#define SSP_CR1_RIE      _BIT(0)      /* RX FIFO interrupt enable */ 
#define SSP_CR1_TIE      _BIT(1)      /* TX FIFO interrupt enable */
#define SSP_CR1_LBM      _BIT(2)      /* Loop back mode */ 
#define SSP_CR1_SPO      _BIT(3)      /* SCLK Polarity */ 
#define SSP_CR1_SPH      _BIT(4)      /* SCLK Phase */ 
#define SSP_CR1_RORIE    _BIT(5)      /* RX Overrun Interrupt Enable */ 
#define SSP_CR1_FEN      _BIT(6)      /* FIFO Enable */ 
#define SSP_CR1_TXIDLE   _BIT(7)      /* TX Idle Interrupt Enable */ 

/**********************************************************************
 * SSP Interrupt Identification / Interrupt Clear Register Bit Fields
 *********************************************************************/ 
#define SSP_IIR_RIS      _BIT(0)      /* TX FIFO Empty */ 
#define SSP_IIR_TIS      _BIT(1)      /* TX FIFO not full */
#define SSP_IIR_RORIS    _BIT(6)      /* RX FIFO overrun int status */ 
#define SSP_IIR_TXIDLE   _BIT(7)      /* TX FIFO empty int status */ 
#define SSP_ICR_CLEAR    0            /* Clear RX FIFO overrun int */ 

/**********************************************************************
 * SSP Clock Prescale Divisor Register Bit Fields
 *********************************************************************/ 
#define SSP_DATAMASK(n)   ((n)&0xFFFF)

/**********************************************************************
 * SSP Clock Prescale Divisor Register Bit Fields
 *********************************************************************/ 
#define   SSP_CPSR_CPDVSR(n) _SBF(0,(n)&0xFE) /* Clock prescale divisor */

/**********************************************************************
 * SSP Status Register Bit Fields
 *********************************************************************/ 
#define SSP_SR_TNF      _BIT(1)      /* TX FIFO not full */
#define SSP_SR_RNE      _BIT(2)      /* RX FIFO not empty */ 
#define SSP_SR_BSY      _BIT(3)      /* SSP Busy */ 
#define SSP_SR_THE      _BIT(4)      /* TX FIFO Half-empty */ 
#define SSP_SR_RHF      _BIT(5)      /* RX FIFO Half-full */ 
#define SSP_SR_ROR      _BIT(6)      /* RX Overrun */ 
#define SSP_SR_TFE      _BIT(7)      /* TX FIFO Empty */ 
#define SSP_SR_RFF      _BIT(8)      /* RX FIFO full */ 

#endif /* LH7A400_SSP_H */