lh7a400_evb.h

sharp flash blob 的烧写代码

/**********************************************************************
 *   $Workfile:   LH7A400_evb.h  $
 *   $Revision:   1.23  $
 *   $Author:   MaysR  $
 *   $Date:   Aug 27 2002 11:39:06  $
 *
 *   Project: LH7A400 Evaluation Board (EVB)
 *
 *   Description:
 *      This file contains the following information for the
 *      LH7A400 Evaluation Board Platform (EVB):
 *
 *         Includes the LH7A400 Map file
 *         Includes EVB-specific include files which include:
 *            EVB-specific primitive include files
 *            EVB-specific function prototype declarations
 *            EVB-specific function manifest constants
 *         Declares for EVB-specific typedefs
 *         Defines for EVB-specific manifest constants
 *         Defines for EVB-specific manifest macros
 *         Defines for EVB-specific conditional constants
 *         Notes on specific EVB usage
 *
 *   References:
 *      (1) Sharp LH7A400 Universal Microcontroller User's Guide,
 *      Version 1.x, Sharp Microelectronics of the Americas, Inc.
 *      (2) Product Specification for Sharp LH7A400 Evaluation and
 *      Development Board, Revision -02,
 *
 *   Revision History:
 *   $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Platform/LH7A400_evb.h-arc  $
 * 
 *    Rev 1.23   Aug 27 2002 11:39:06   MaysR
 * Removed invalid reference to non-existent bit in BCR register.
 * Increased wait states of BCR3 for sequential and read/write to
 * 18.  Also increased turn around delay for BCR3 to 2.
 * 
 *    Rev 1.22   Aug 21 2002 19:42:22   MaysR
 * Increased WST1 for bcr3.  Old value was to fast.
 * 
 *    Rev 1.21   Aug 20 2002 17:15:10   MaysR
 * Changed SMC->bcr3 defaults for Ethernet interface default.
 * 
 *    Rev 1.20   Jul 30 2002 19:03:04   BarnettH
 * Added DIPSW Interpretation
 * 
 *    Rev 1.19   Jun 25 2002 18:41:10   BarnettH
 * Added prototypes for get_dipsw and copylongs
 * 
 *    Rev 1.18   Jun 14 2002 13:32:12   BarnettH
 * Moved all CLKSET definitions to LH7A400_clksc.h file.
 * Eliminated CLKIDX definitions
 * Cleaned up file banner.
 * Removed PROTO_LH7A400 conditional.
 * Redefined SVC_STACK_BASE
 * 
 *    Rev 1.17   Jun 06 2002 10:12:26   BarnettH
 * Changed LED constant names to match Rev. 2 board
 * 
 *    Rev 1.16   Jun 05 2002 10:30:22   MaysR
 * Cleaned up CPLD bit defines.
 * 
 * Added additional clock indexes.
 * 
 *    Rev 1.15   May 22 2002 10:08:58   MaysR
 * Changed BCR0 settings back for Async flash compatability.
 * 
 * 
 *    Rev 1.14   May 21 2002 18:16:30   MaysR
 * Added new clock defines for 184/92/46 & 190/96/48.
 * 
 * Changed clock default to 200/100/50.
 * 
 * Changed default values of BCR1 to work with B.0 silicon + one to be conservative.
 * 
 *    Rev 1.13   Apr 18 2002 17:26:46   KovitzP
 * Enabled page mode access for boot block flash.
 * 
 *    Rev 1.12   02 Apr 2002 11:53:42   kovitzp
 * Added legal disclaimer.
 * 
 *    Rev 1.11   Jan 03 2002 17:52:36   KovitzP
 * Moved CPLD bit definitions here.
 * 
 *    Rev 1.10   Jan 02 2002 09:25:42   KovitzP
 * Added SMC_SRAM_32_BITS define constant (instead of
 * commented-out code).
 * 
 * Stripped out tab characters and the PACKED predefine.
 * 
 *    Rev 1.9   Nov 30 2001 11:26:44   WellsK
 * Added MMU init table definition for SDRAM cached at
 * address 0x0.
 * 
 *    Rev 1.8   Nov 16 2001 16:47:46   MaysR
 * Added predefine for IRAM mapped to zero.
 *
 *    Rev 1.7   Nov 14 2001 16:36:52   MaysR
 * Changed SRAM BCR1 configuration for 16bit mode.   Added wait states for stability at higher speeds (preliminary, needs more testing).  Added additional clock speed settings up to 200-100-50.
 *
 *    Rev 1.6   Oct 24 2001 09:41:34   BarnettH
 * Removed "..._sevenseg.h" include
 *
 *    Rev 1.5   Oct 04 2001 18:11:16   BarnettH
 * Added pre-define PROTO_LH7A400 to establish default clock settings for the prototype chip.
 * Added pre-define USE_OS_TIMER_2 for switching the OS timer to Timer 2.
 *
 *    Rev 1.4   Oct 02 2001 14:37:20   BarnettH
 * Changed BCRx constants to lh7A400_smc definitions
 *
 *    Rev 1.3   Oct 01 2001 17:50:02   BarnettH
 * Changed lcd_pwr_ctl identifier to lcd_pwr_cntl
 *
 *    Rev 1.2   Sep 28 2001 15:11:02   BarnettH
 * Moved _BIT and _SBF definitions to SMA_types.h
 * Corrected CLKSET_66_33_8 coding error.
 * Added several clock sets and indices up to 200 MHz core
 * Added OS manifest constants.
 * Added malloc() manifest constants.
 *
 *    Rev 1.1   Sep 18 2001 13:35:02   SuryanG
 * Added CPLD structure.
 *
 *    Rev 1.0   Sep 18 2001 13:05:12   BarnettH
 * Preliminary revision.
 *
 ***********************************************************************
 * 
 *  Copyright (c) 2002 Sharp Microelectronics of the Americas
 *
 *  All rights reserved
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 **********************************************************************/
#ifndef LH7A400_EVB_H
#define LH7A400_EVB_H

#if defined (__cplusplus)
extern "C" {
#endif

#ifndef MMU_MAP_SRAM_0
#define MMU_MAP_SRAM_0
#endif
/***********************************************************************
 * Library header files (#include)
 **********************************************************************/

/***********************************************************************
 * User header files (#include)
 **********************************************************************/
#include "SMA_types.h"
#include "LH7A400_map.h"

/***********************************************************************
 * Constant definitions (#define)
 **********************************************************************/

/**********************************************************************
 *** Asynchronous Memory Controller Initialization codes
 *********************************************************************/
#define SMC_BCR0_INIT   (SMC_BCR_MW32 | SMC_BCR_WST2(8) | \
                        SMC_BCR_WST1(3) | SMC_BCR_IDCY(1))// | \
                        SMC_BCR_PME) 

#if defined SMC_SRAM_32_BITS
#define SMC_BCR1_INIT   (SMC_BCR_MW32 | SMC_BCR_WST2(2) | \
                        SMC_BCR_WST1(3) | SMC_BCR_IDCY(1))
#else
#define SMC_BCR1_INIT   (SMC_BCR_MW16 | SMC_BCR_WST2(2) | \
                        SMC_BCR_WST1(3) | SMC_BCR_IDCY(1))
#endif

#define SMC_BCR2_INIT   (SMC_BCR_MW8 | SMC_BCR_WST2(31) | \
                        SMC_BCR_WST1(31))

#define SMC_BCR3_INIT   (SMC_BCR_MW16 | SMC_BCR_IDCY(2) |  \
                         SMC_BCR_WST1(18)| SMC_BCR_WST2(18))

/**********************************************************************
 *** CPLD
 *********************************************************************/

#define CPLD_BASE   (SMC_CS2_BASE)

typedef struct
{
    union
    {
        volatile UNS_8 rd_opt_dip_sw;
        volatile UNS_8 wr_io_brd_ctl;
    } control;
    volatile UNS_8 reserved1;
    volatile UNS_8 rd_pb_keys;
    volatile UNS_8 reserved2;
    volatile UNS_8 latched_ints;
    volatile UNS_8 reserved3;
    volatile UNS_8 boot_mmc_status;
    volatile UNS_8 reserved4;
    union
    {
        volatile UNS_16 rd_kpd_row_sense;
        struct
        {
            volatile UNS_8 wr_pb_int_mask;
            volatile UNS_8 reserved5;
        } intmask;
    } status;
    union
    {
        volatile UNS_8 rd_disp_brd_sw;
        volatile UNS_8 wr_ext_int_mask;
    } extsettings;
    volatile UNS_8 reserved6;
    volatile UNS_8 lcd_pwr_cntl;
    volatile UNS_8 reserved7;
    volatile UNS_16 seven_seg;
} CPLDREGS;

#define CPLD    ((CPLDREGS *)(CPLD_BASE))

/* I/O board power control register bit definitions */
#define CPLD_PC1_P1                     _BIT(0)
#define CPLD_PC1_P2                     _BIT(1)
#define CPLD_PC2_P1                     _BIT(2)
#define CPLD_PC2_P2                     _BIT(3)
#define CPLD_AC97_PWR                   _BIT(4)
#define CPLD_I2S_PWR                    _BIT(5)
#define CPLD_ETH_SLEEP                  _BIT(6)
#define CPLD_MMC_PWR                    _BIT(7)

/* Push button switch register bit definitions */
#define CPLD_PB_SW10                    _BIT(0)
#define CPLD_PB_SW11                    _BIT(1)
#define CPLD_PB_SW12                    _BIT(2)
#define CPLD_PB_SW13                    _BIT(3)
#define CPLD_PB_SW14                    _BIT(4)
#define CPLD_PB_SW15                    _BIT(5)
#define CPLD_PB_SW16                    _BIT(6)
#define CPLD_PB_SW17                    _BIT(7)

/* Latched interrupt event register bit definitions */
#define CPLD_MMC_CD_INT                 _BIT(0)
#define CPLD_RI2_INT                    _BIT(1)
#define CPLD_CF_IDE_INT                 _BIT(2)
#define CPLD_ETH_INT                    _BIT(3)
#define CPLD_SW3_INT                    _BIT(4)

/* Boot device & MMC status register bit definitions */
#define CPLD_MMC_CARD_PRESENT           _BIT(0)
#define CPLD_MMC_CARD_WP                _BIT(1)
#define CPLD_BOOT_DEV_FLASH             _BIT(4)
#define CPLD_BOOT_DEV_SYNCFLASH         _BIT(5)
#define CPLD_BOOT_DEV_SRAM              _BIT(6)

/* LCD power control register bit definitions */
#define CPLD_LCD_nSHUT                  _BIT(0)
#define CPLD_LCD_BKLT                   _BIT(1)
#define CPLD_LCD_DISP_E                 _BIT(2)
#define CPLD_LCD_OE                     _BIT(3)
#define CPLD_LCD_LOW_VOLT_EN            _BIT(4)

/***********************************************************************
 * DIPSW Interpretation 
 **********************************************************************/
// Values correlate to arguments for LH7A400_evb_get_dipsw ()
#define DIPSW_CPU       0
#define DIPSW_DISP      1
// Values correlate to Major Modes
#define DIPSW_EIT               0
#define DIPSW_RAM_DEBUG         1
#define DIPSW_RAM_USER          2
#define DIPSW_RAM_DEMOA         4
#define DIPSW_RAM_DEMOB         6
// Values correlate to EIT Minor Modes
#define DIPSW_EIT_ALL           0
#define DIPSW_EIT_SPECIFIC      1
#define DIPSW_EIT_MEM_ONLY      7
// Values correlate to RAM Debug Minor Modes
#define DIPSW_RAM_DEBUG_NORMAL  0
#define DIPSW_RAM_DEBUG_ALT1    1
#define DIPSW_RAM_DEBUG_ALT2    2
#define DIPSW_RAM_DEBUG_NOINIT  7

/***********************************************************************
 * System Clock 
 * LH7A400_BASE_CLOCK is defined in LH7A400_clksc.h as 14745600 Hz
 **********************************************************************/

/***********************************************************************
 * Default Clock Set code
 * Overrides CLKSET_DEFAULT defined in LH7A400_clksc.h
 **********************************************************************/

#ifdef PROTO_LH7A400
#undef CLKSET_DEFAULT
#define CLKSET_DEFAULT      CLKSET_66_66_33
#else
#undef CLKSET_DEFAULT
#define CLKSET_DEFAULT      CLKSET_200_100_50
#endif

/***********************************************************************
 *    malloc() Constants
 * Warning: these values must be coherent with the values set by the
 * startup code or initialization code, as applicable.
 * Note that SVC_STACK_INIT may be set by either the startup code or
 * the crt0 code.
 * See LH7A400_evb.i and crt0.s for additional information.
 **********************************************************************/
/* Assumes 64 MB SDRAM, SDRAM mapped to 0x0 base */
#define LH7A400_EVB_SDRAM_LIMIT 0x04000000
/* Assumes Supervisor Stack is the top stack at top of SDRAM (FD) */
#define SVC_STACK_BASE          LH7A400_EVB_SDRAM_LIMIT

/***********************************************************************
 * LED Constants
 **********************************************************************/
#define LED_D16            _BIT(1)
#define LED_D17            _BIT(2)
#define LED_ON             0
#define LED_OFF            1
#define LED_TOGGLE         2

/***********************************************************************
 * Identify which Translation Table initialization data to use
 **********************************************************************/
#define MMU_LEVEL1_DESCRIPTORS   tt_init_basic

/***********************************************************************
 * Global function prototypes
 **********************************************************************/
UNS_32 LH7A400_evb_get_dipsw (UNS_32 mode);
INT_32 SMA_copylongs (UNS_32 length,
                      UNS_32 * source,
                      UNS_32 * destination);

/***********************************************************************
 * Put User Entries below this line
 **********************************************************************/

/* zzz TBD Needs to be reviewed */ 
#ifdef MMU_MAP_SRAM_0
#undef MMU_LEVEL1_DESCRIPTORS
#define MMU_LEVEL1_DESCRIPTORS tt_init_sram_at_0
#else
#ifdef IRAMATZERO

#undef MMU_LEVEL1_DESCRIPTORS
#define MMU_LEVEL1_DESCRIPTORS tt_sdram_open_iram_at_0

#else

#ifdef CACHED_SDRAM_AT_0
#undef MMU_LEVEL1_DESCRIPTORS
#define MMU_LEVEL1_DESCRIPTORS tt_cached_sdram_at_0
#endif

#endif
#endif

#if defined (__cplusplus)
}
#endif

#endif /* LH7A400_EVB_H */