📄 lh7a400_sci.h
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/**********************************************************************
* $Workfile: LH7A400_sci.h $
* $Revision: 1.1 $
* $Author: MaysR $
* $Date: Aug 29 2002 09:04:32 $
*
* Project: LH7A400 headers
*
* Description:
* This file contains the structure definitions and manifest
* constants for LH7A400 component:
* Smart Card Interface
*
* References:
* (1) Sharp LH7A400 Universal SoC User's Guide
*
* Revision History:
* $Log: //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/LH7A400_sci.h-arc $
*
* Rev 1.1 Aug 29 2002 09:04:32 MaysR
* Renamed register structure names and most bit definitions.
*
* Rev 1.0 Jun 20 2002 11:06:14 MaysR
* Initial revision.
*
*
* SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
* OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
* AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
* SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
*
* SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
* FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
* SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
* FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
*
* COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
* CAMAS, WA
*********************************************************************/
#ifndef LH7A400_SCI_H
#define LH7A400_SCI_H
#include "SMA_types.h"
/* SCI Register Structure */
typedef struct
{
volatile UNS_32 data; /* Data register */
volatile UNS_32 cr0; /* Control register zero */
volatile UNS_32 cr1; /* Control register one */
volatile UNS_32 cr2; /* Control register two */
volatile UNS_32 ier; /* Interrupt Enable register */
volatile UNS_32 retry; /* Retry Limit register */
volatile UNS_32 wmark; /* FIFO Tide water mark register */
volatile UNS_32 txcount; /* TX FIFO Count Clear register */
volatile UNS_32 rxcount; /* TX FIFO Count Clear register */
volatile UNS_32 fr; /* FIFO status register */
volatile UNS_32 rxtime; /* Receive Read timeout register */
volatile UNS_32 dstat; /* Direct Status register */
volatile UNS_32 stable; /* De-Bounce timer register */
volatile UNS_32 atime; /* Activation Event Timer reg */
volatile UNS_32 dtime; /* Deactivation Event Timer reg */
volatile UNS_32 atrstime; /* Time To Start ATR RX register */
volatile UNS_32 atrdtime; /* ATD Max char Duration reg */
volatile UNS_32 blktime; /* Block to Block RX TimeOut */
volatile UNS_32 chtime; /* Char to Char RX TimeOut */
volatile UNS_32 clkdiv; /* External Clock Frequency */
volatile UNS_32 baud; /* Baud rate clock register */
volatile UNS_32 cycles; /* Baud Cycles register */
volatile UNS_32 chguard; /* Char to Char extra guard time */
volatile UNS_32 blkguard; /* Block Guard Time register */
volatile UNS_32 synccr; /* Sync/Async mux control reg */
volatile UNS_32 syncdata; /* Sync Data register */
volatile UNS_32 rawstat; /* Raw I/O & clock status reg */
volatile UNS_32 iir_icr; /* Interrupt ID / Clear reg */
volatile UNS_32 control; /* Enable & Pre-Divide register */
}SCIREGS;
/**********************************************************************
* Data Register Bit Fields
*********************************************************************/
#define SCI_DATA(n) _SBF(0, (n & 0xFF))
#define SCI_PARITY _BIT(8)
/**********************************************************************
* Control Register Zero Bit Fields
*********************************************************************/
#define SCI_SENSE _BIT(0)
#define SCI_ORDER _BIT(1)
#define SCI_TXPARITY _BIT(2)
#define SCI_TXNAK _BIT(3)
#define SCI_RXPARITY _BIT(4)
#define SCI_RXNAK _BIT(5)
/**********************************************************************
* Control Register One Bit Fields
*********************************************************************/
#define SCI_ATRDEN _BIT(0)
#define SCI_BLKEN _BIT(1)
#define SCI_MODE _BIT(2)
#define SCI_CLKZ1 _BIT(3)
#define SCI_BGTEN _BIT(4)
#define SCI_EXDBNCE _BIT(5)
/**********************************************************************
* Control Register Two Bit Fields
*********************************************************************/
#define SCI_STARTUP _BIT(0)
#define SCI_FINISH _BIT(1)
#define SCI_WRESET _BIT(2)
/**********************************************************************
* Interrupt Enable Register Bit Fields
*********************************************************************/
#define SCI_CARDINIE _BIT(0)
#define SCI_CARDOUTIE _BIT(1)
#define SCI_CARDUPIE _BIT(2)
#define SCI_CARDDNIE _BIT(3)
#define SCI_TXERRIE _BIT(4)
#define SCI_ATRSTOUTIE _BIT(5)
#define SCI_ATRDTOUTIE _BIT(6)
#define SCI_BLKTOIE _BIT(7)
#define SCI_CHTOUTIE _BIT(8)
#define SCI_RTOUTIE _BIT(9)
#define SCI_RXWMARKIE _BIT(10)
#define SCI_TXWMARKIE _BIT(11)
/**********************************************************************
* Retry Register Bit Fields
*********************************************************************/
#define SCI_TXRETRY(n) _SBF(0, (n & 0x7))
#define SCI_RXRETRY(n) _SBF(3, (n & 0x7))
/**********************************************************************
* FIFO Watermark Register Bit Fields
*********************************************************************/
#define SCI_RXWMARK(n) _SBF(0, (n & 0xF))
#define SCI_TXWMARK(n) _SBF(4, (n & 0xF))
/**********************************************************************
* TX FIFO Count Register Bit Fields
*********************************************************************/
#define SCI_TXCOUNTCLR _BIT(0) // WO
#define SCI_TXCOUNT(n) _SBF(0, (n & 0x1F)) // RO
/**********************************************************************
* RX FIFO Count Register Bit Fields
*********************************************************************/
#define SCI_RXCOUNTCLR _BIT(0) // WO
#define SCI_RXCOUNT(n) _SBF(0, (n & 0x1F)) // RO
/**********************************************************************
* Flag Register Bit Fields
*********************************************************************/
#define SCI_TXFF _BIT(0)
#define SCI_TXFE _BIT(1)
#define SCI_RXFF _BIT(2)
#define SCI_RXFE _BIT(3)
/**********************************************************************
* RX Read Timeout Register Bit Fields
*********************************************************************/
#define SCI_RXTIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* ICC Status Register Bit Fields
*********************************************************************/
#define SCI_POWER _BIT(0)
#define SCI_CRESET _BIT(1)
#define SCI_CLKEN _BIT(2)
#define SCI_DATAEN _BIT(3)
#define SCI_CLKOUTEN _BIT(4)
#define SCI_CLKENB _BIT(5)
#define SCI_CLKOUT _BIT(6)
#define SCI_DATAOUTEN _BIT(7)
#define SCI_DATAENB _BIT(8)
#define SCI_CARDPRESENT _BIT(9)
/**********************************************************************
* Debounce Timer Register Bit Field
*********************************************************************/
#define SCI_STABLE(n) _SBF(0, (n & 0xFF))
/**********************************************************************
* Activation Time Event Register Bit Field
*********************************************************************/
#define SCI_ATIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* Deactivation Time Register Bit Field
*********************************************************************/
#define SCI_DTIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* Time to ATR reception Register Bit Field
*********************************************************************/
#define SCI_ATRSTIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* ATR Duration Timeout Register Bit Field
*********************************************************************/
#define SCI_ATRDTIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* RX Block to Block Timeout Register Bit Field
*********************************************************************/
#define SCI_BLKTIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* RX Char to Char Timeout Register Bit Field
*********************************************************************/
#define SCI_CHTIME(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* Char Clock Divider Register Bit Field
*********************************************************************/
#define SCI_CLKDIV(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* Baud Rate Clock Register Bit Field
*********************************************************************/
#define SCI_BAUD(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* Baud Cycle Register Bit Field
*********************************************************************/
#define SCI_BAUD_CYC(n) _SBF(0, (n & 0xFFFF))
/**********************************************************************
* Char to Char Guard Time Register Bit Field
*********************************************************************/
#define SCI_CHGUARD(n) _SBF(0, (n & 0xFF))
/**********************************************************************
* Block to Block Guard Time Register Bit Field
*********************************************************************/
#define SCI_BLKGUARD(n) _SBF(0, (n & 0xFF))
/**********************************************************************
* Sync / Async Select Register Bit Field
*********************************************************************/
#define SCI_SELDATA _BIT(0)
#define SCI_SELCLK _BIT(1)
/**********************************************************************
* Sync Data Select Register Bit Field
*********************************************************************/
#define SCI_WDATA _BIT(0)
#define SCI_WCLK _BIT(1)
#define SCI_WDATAEN _BIT(2)
#define SCI_WCLKEN _BIT(3)
/**********************************************************************
* Raw Clock Status Register Bit Field
*********************************************************************/
#define SCI_RDATA _BIT(0)
#define SCI_RCLK _BIT(1)
/**********************************************************************
* Interrupt Raw Status / Clear Register Bit Fields
*********************************************************************/
#define SCI_CARDININTR_BIT (0)
#define SCI_CARDOUTINTR_BIT (1)
#define SCI_CARDUPINTR_BIT (2)
#define SCI_CARDDNINTR_BIT (3)
#define SCI_TXERRINTR_BIT (4)
#define SCI_ATRSTOUTINTR_BIT (5)
#define SCI_ATRDTOUTINTR_BIT (6)
#define SCI_BLKTOUTINTR_BIT (7)
#define SCI_CHTOUTINTR_BIT (8)
#define SCI_RTOUTINTR_BIT (9)
#define SCI_RXWMARKINTR_BIT (10)
#define SCI_TXWMARKINTR_BIT (11)
#define SCI_CARDININTR _BIT(SCI_CARDININTR_BIT)
#define SCI_CARDOUTINTR _BIT(SCI_CARDOUTINTR_BIT)
#define SCI_CARDUPINTR _BIT(SCI_CARDUPINTR_BIT)
#define SCI_CARDDNINTR _BIT(SCI_CARDDNINTR_BIT)
#define SCI_TXERRINTR _BIT(SCI_TXERRINTR_BIT)
#define SCI_ATRSTOUTINTR _BIT(SCI_ATRSTOUTINTR_BIT)
#define SCI_ATRDTOUTINTR _BIT(SCI_ATRDTOUTINTR_BIT)
#define SCI_BLKTOUTINTR _BIT(SCI_BLKTOUTINTR_BIT)
#define SCI_CHTOUTINTR _BIT(SCI_CHTOUTINTR_BIT)
#define SCI_RTOUTINTR _BIT(SCI_RTOUTINTR_BIT)
#define SCI_RXWMARKINTR _BIT(SCI_RXWMARKINTR_BIT)
#define SCI_TXWMARKINTR _BIT(SCI_TXWMARKINTR_BIT)
#define SCI_CLEARALLINTS _SBF(0, (SCI_CARDININTR | \
SCI_CARDOUTINTR | \
SCI_CARDUPINTR | \
SCI_CARDDNINTR | \
SCI_TXERRINTR | \
SCI_ATRSTOUTINTR | \
SCI_ATRDTOUTINTR | \
SCI_BLKTOUTINTR | \
SCI_CHTOUTINTR | \
SCI_RTOUTINTR | \
SCI_RXWMARKINTR | \
SCI_TXWMARKINTR))
/**********************************************************************
* Control Register Bit Field
*********************************************************************/
#define SCI_EN _BIT(0)
#define SCI_PREDIV _BIT(1)
#define SCI_MUX_VCCEN _BIT(4)
#define SCI_MUX_DETECT _BIT(5)
#endif /* LH7A400_SCI_H */
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