md.texi

gcc库的原代码,对编程有很大帮助.

@table @code
@item f
Floating point register (@code{fp0} to @code{fp3})

@item l
Local register (@code{r0} to @code{r15})

@item b
Global register (@code{g0} to @code{g15})

@item d
Any local or global register

@item I
Integers from 0 to 31

@item J
0

@item K
Integers from -31 to 0

@item G
Floating point 0

@item H
Floating point 1
@end table

@item MIPS---@file{mips.h}
@table @code
@item d
General-purpose integer register

@item f
Floating-point register (if available)

@item h
@samp{Hi} register

@item l
@samp{Lo} register

@item x
@samp{Hi} or @samp{Lo} register

@item y
General-purpose integer register

@item z
Floating-point status register

@item I
Signed 16 bit constant (for arithmetic instructions)

@item J
Zero

@item K
Zero-extended 16-bit constant (for logic instructions)

@item L
Constant with low 16 bits zero (can be loaded with @code{lui})

@item M
32 bit constant which requires two instructions to load (a constant
which is not @samp{I}, @samp{K}, or @samp{L})

@item N
Negative 16 bit constant

@item O
Exact power of two

@item P
Positive 16 bit constant

@item G
Floating point zero

@item Q
Memory reference that can be loaded with more than one instruction
(@samp{m} is preferable for @code{asm} statements)

@item R
Memory reference that can be loaded with one instruction
(@samp{m} is preferable for @code{asm} statements)

@item S
Memory reference in external OSF/rose PIC format
(@samp{m} is preferable for @code{asm} statements)
@end table

@item Motorola 680x0---@file{m68k.h}
@table @code
@item a
Address register

@item d
Data register

@item f
68881 floating-point register, if available

@item x
Sun FPA (floating-point) register, if available

@item y
First 16 Sun FPA registers, if available

@item I
Integer in the range 1 to 8

@item J
16 bit signed number

@item K
Signed number whose magnitude is greater than 0x80

@item L
Integer in the range -8 to -1

@item G
Floating point constant that is not a 68881 constant

@item H
Floating point constant that can be used by Sun FPA
@end table

@need 1000
@item SPARC---@file{sparc.h}
@table @code
@item f
Floating-point register

@item I
Signed 13 bit constant

@item J
Zero

@item K
32 bit constant with the low 12 bits clear (a constant that can be
loaded with the @code{sethi} instruction)

@item G
Floating-point zero

@item H
Signed 13 bit constant, sign-extended to 32 or 64 bits

@item Q
Memory reference that can be loaded with one instruction  (@samp{m} is
more appropriate for @code{asm} statements)

@item S
Constant, or memory address

@item T
Memory address aligned to an 8-byte boundary

@item U 
Even register
@end table
@end table

@ifset INTERNALS
@node No Constraints
@subsection Not Using Constraints
@cindex no constraints
@cindex not using constraints

Some machines are so clean that operand constraints are not required.  For
example, on the Vax, an operand valid in one context is valid in any other
context.  On such a machine, every operand constraint would be @samp{g},
excepting only operands of ``load address'' instructions which are
written as if they referred to a memory location's contents but actual
refer to its address.  They would have constraint @samp{p}.

@cindex empty constraints
For such machines, instead of writing @samp{g} and @samp{p} for all
the constraints, you can choose to write a description with empty constraints.
Then you write @samp{""} for the constraint in every @code{match_operand}.
Address operands are identified by writing an @code{address} expression
around the @code{match_operand}, not by their constraints.

When the machine description has just empty constraints, certain parts
of compilation are skipped, making the compiler faster.  However,
few machines actually do not need constraints; all machine descriptions
now in existence use constraints.
@end ifset

@ifset INTERNALS
@node Standard Names
@section Standard Pattern Names For Generation
@cindex standard pattern names
@cindex pattern names
@cindex names, pattern

Here is a table of the instruction names that are meaningful in the RTL
generation pass of the compiler.  Giving one of these names to an
instruction pattern tells the RTL generation pass that it can use the
pattern in to accomplish a certain task.

@table @asis
@cindex @code{mov@var{m}} instruction pattern
@item @samp{mov@var{m}}
Here @var{m} stands for a two-letter machine mode name, in lower case.
This instruction pattern moves data with that machine mode from operand
1 to operand 0.  For example, @samp{movsi} moves full-word data.

If operand 0 is a @code{subreg} with mode @var{m} of a register whose
own mode is wider than @var{m}, the effect of this instruction is
to store the specified value in the part of the register that corresponds
to mode @var{m}.  The effect on the rest of the register is undefined.

This class of patterns is special in several ways.  First of all, each
of these names @emph{must} be defined, because there is no other way
to copy a datum from one place to another.

Second, these patterns are not used solely in the RTL generation pass.
Even the reload pass can generate move insns to copy values from stack
slots into temporary registers.  When it does so, one of the operands is
a hard register and the other is an operand that can need to be reloaded
into a register.

@findex force_reg
Therefore, when given such a pair of operands, the pattern must generate
RTL which needs no reloading and needs no temporary registers---no
registers other than the operands.  For example, if you support the
pattern with a @code{define_expand}, then in such a case the
@code{define_expand} mustn't call @code{force_reg} or any other such
function which might generate new pseudo registers.

This requirement exists even for subword modes on a RISC machine where
fetching those modes from memory normally requires several insns and
some temporary registers.  Look in @file{spur.md} to see how the
requirement can be satisfied.

@findex change_address
During reload a memory reference with an invalid address may be passed
as an operand.  Such an address will be replaced with a valid address
later in the reload pass.  In this case, nothing may be done with the
address except to use it as it stands.  If it is copied, it will not be
replaced with a valid address.  No attempt should be made to make such
an address into a valid address and no routine (such as
@code{change_address}) that will do so may be called.  Note that
@code{general_operand} will fail when applied to such an address.

@findex reload_in_progress
The global variable @code{reload_in_progress} (which must be explicitly
declared if required) can be used to determine whether such special
handling is required.

The variety of operands that have reloads depends on the rest of the
machine description, but typically on a RISC machine these can only be
pseudo registers that did not get hard registers, while on other
machines explicit memory references will get optional reloads.

If a scratch register is required to move an object to or from memory,
it can be allocated using @code{gen_reg_rtx} prior to reload.  But this
is impossible during and after reload.  If there are cases needing
scratch registers after reload, you must define
@code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
@code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
them.  @xref{Register Classes}.

The constraints on a @samp{move@var{m}} must permit moving any hard
register to any other hard register provided that
@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
@code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.

It is obligatory to support floating point @samp{move@var{m}}
instructions into and out of any registers that can hold fixed point
values, because unions and structures (which have modes @code{SImode} or
@code{DImode}) can be in those registers and they may have floating
point members.

There may also be a need to support fixed point @samp{move@var{m}}
instructions in and out of floating point registers.  Unfortunately, I
have forgotten why this was so, and I don't know whether it is still
true.  If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
floating point registers, then the constraints of the fixed point
@samp{move@var{m}} instructions must be designed to avoid ever trying to
reload into a floating point register.

@cindex @code{reload_in} instruction pattern
@cindex @code{reload_out} instruction pattern
@item @samp{reload_in@var{m}}
@itemx @samp{reload_out@var{m}}
Like @samp{mov@var{m}}, but used when a scratch register is required to
move between operand 0 and operand 1.  Operand 2 describes the scratch
register.  See the discussion of the @code{SECONDARY_RELOAD_CLASS}
macro in @pxref{Register Classes}.

@cindex @code{movstrict@var{m}} instruction pattern
@item @samp{movstrict@var{m}}
Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
with mode @var{m} of a register whose natural mode is wider,
the @samp{movstrict@var{m}} instruction is guaranteed not to alter
any of the register except the part which belongs to mode @var{m}.

@cindex @code{load_multiple} instruction pattern
@item @samp{load_multiple}
Load several consecutive memory locations into consecutive registers.
Operand 0 is the first of the consecutive registers, operand 1
is the first memory location, and operand 2 is a constant: the
number of consecutive registers.

Define this only if the target machine really has such an instruction;
do not define this if the most efficient way of loading consecutive
registers from memory is to do them one at a time.

On some machines, there are restrictions as to which consecutive
registers can be stored into memory, such as particular starting or
ending register numbers or only a range of valid counts.  For those
machines, use a @code{define_expand} (@pxref{Expander Definitions})
and make the pattern fail if the restrictions are not met.

Write the generated insn as a @code{parallel} with elements being a
@code{set} of one register from the appropriate memory location (you may
also need @code{use} or @code{clobber} elements).  Use a
@code{match_parallel} (@pxref{RTL Template}) to recognize the insn.  See
@file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
pattern.

@cindex @samp{store_multiple} instruction pattern
@item @samp{store_multiple}
Similar to @samp{load_multiple}, but store several consecutive registers
into consecutive memory locations.  Operand 0 is the first of the
consecutive memory locations, operand 1 is the first register, and
operand 2 is a constant: the number of consecutive registers.

@cindex @code{add@var{m}3} instruction pattern
@item @samp{add@var{m}3}
Add operand 2 and operand 1, storing the result in operand 0.  All operands
must have mode @var{m}.  This can be used even on two-address machines, by
means of constraints requiring operands 1 and 0 to be the same location.

@cindex @code{sub@var{m}3} instruction pattern
@cindex @code{mul@var{m}3} instruction pattern
@cindex @code{div@var{m}3} instruction pattern
@cindex @code{udiv@var{m}3} instruction pattern
@cindex @code{mod@var{m}3} instruction pattern
@cindex @code{umod@var{m}3} instruction pattern
@cindex @code{min@var{m}3} instruction pattern
@cindex @code{max@var{m}3} instruction pattern
@cindex @code{umin@var{m}3} instruction pattern
@cindex @code{umax@var{m}3} instruction pattern
@cindex @code{and@var{m}3} instruction pattern
@cindex @code{ior@var{m}3} instruction pattern
@cindex @code{xor@var{m}3} instruction pattern
@item @samp{sub@var{m}3}, @samp{mul@