1750a.md

gcc库的原代码,对编程有很大帮助.

  ""
  "slr r%0,r%2 ")

;; Same thing for HImode.

(define_expand "lshrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:QI 2 "nonmemory_operand" "g")))]
  ""
  "
  {
    if (GET_CODE (operands[2]) != CONST_INT)
      operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
  }")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:QI 2 "immediate_operand" "L")))]
  ""
  "*
  {
    rtx new_opnds[2];
    int amount = INTVAL(operands[2]);
    if (amount <= 16)
      return \"dsrl r%0,%2\";
    output_asm_insn(\"dsrl r%0,16  ; lshrhi3 shiftcount > 16\",operands);
    new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1);
    new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16);
    output_asm_insn(\"srl  r%0,%1\",new_opnds);
    return \";\";
  } ")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "dslr r%0,r%2 ")

;; Same applies for arithmetic shift right.
(define_expand "ashrqi3"
  [(set (match_operand:QI 0 "general_operand" "=r")
	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
		     (match_operand:QI 2 "nonmemory_operand" "g")))]
  ""
  "
  {
    if (GET_CODE (operands[2]) != CONST_INT)
      operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
  }")

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
		     (match_operand:QI 2 "immediate_operand" "I")))]
  ""
  "sra r%0,%2")

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "sar r%0,r%2 ")

;; HImode arithmetic shift right.
(define_expand "ashrhi3"
  [(set (match_operand:HI 0 "general_operand" "=r")
	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:QI 2 "nonmemory_operand" "g")))]
  ""
  "
  {
    if (GET_CODE (operands[2]) != CONST_INT)
      operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
  }")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:QI 2 "immediate_operand" "L")))]
  ""
  "*
  {
    rtx new_opnds[2];
    int amount = INTVAL(operands[2]);
    if (amount <= 16)
      return \"dsra r%0,%2\";
    output_asm_insn(\"dsra r%0,16  ; ashrhi3 shiftcount > 16\",operands);
    new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1);
    new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16);
    output_asm_insn(\"sra  r%0,%1\",new_opnds);
    return \";\";
  } ")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "dsar r%0,r%2 ")


;; rotate instructions

(define_insn "rotlqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "nonmemory_operand" "I,r")))]
  ""
  "@
    slc r%0,%2
    scr r%0,r%2 ")

(define_insn "rotlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "nonmemory_operand" "I,r")))]
  ""
  "@
    dslc r%0,%2
    dscr r%0,r%2 ")

(define_insn "rotrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (rotatert:QI (match_operand:QI 1 "register_operand" "0")
                     (match_operand:QI 2 "register_operand" "r")))]
  ""
  "neg r%2,r%2\;scr r%0,r%2 ")

(define_insn "rotrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (rotatert:HI (match_operand:HI 1 "register_operand" "0")
                     (match_operand:QI 2 "nonmemory_operand" "r")))]
  ""
  "neg  r%2,r%2\;dscr r%0,r%2 ")



;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
;; These handle aligned 8-bit and 16-bit fields,
;; which can usually be done with move instructions.
;    1750: t.b.d.
;********************

;; Bit field instructions, general cases.
;; "o,d" constraint causes a nonoffsetable memref to match the "o"
;; so that its address is reloaded.

;; (define_insn "extv" ...

;; (define_insn "extzv" ...

;; (define_insn "insv" ...

;; Now recognize bit field insns that operate on registers
;; (or at least were intended to do so).
;[unnamed only]

;; Special patterns for optimizing bit-field instructions.
;**************************************

; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
;  [(set (match_operand:QI 0 "general_operand" "=d")
;        (leu (cc0) (const_int 0)))]
;  ""
;  "* cc_status = cc_prev_status;
;     return \"sls %0\"; ")


;; Basic conditional jump instructions.

(define_insn "beq"
  [(set (pc)
        (if_then_else (eq (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "bne"
  [(set (pc)
        (if_then_else (ne (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "bgt"
  [(set (pc)
        (if_then_else (gt (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "blt"
  [(set (pc)
        (if_then_else (lt (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "bge"
  [(set (pc)
        (if_then_else (ge (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "ble"
  [(set (pc)
        (if_then_else (le (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
  ")


; no unsigned branches available on 1750. But GCC still needs them, so faking:

(define_insn "bgtu"
  [(set (pc)
        (if_then_else (gtu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "jc gt,%l0 ; Warning: this should be an *unsigned* test!")

(define_insn "bltu"
  [(set (pc)
        (if_then_else (ltu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "jc lt,%l0 ; Warning: this should be an *unsigned* test!")

(define_insn "bgeu"
  [(set (pc)
        (if_then_else (geu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "jc ge,%l0 ; Warning: this should be an *unsigned* test!")

(define_insn "bleu"
  [(set (pc)
        (if_then_else (leu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "jc le,%l0 ; Warning: this should be an *unsigned* test!")


;; Negated conditional jump instructions.

(define_insn ""
  [(set (pc)
        (if_then_else (eq (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (gt (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (lt (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (ge (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (le (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
  ")


;; Negated unsigned conditional jump instructions (faked for 1750).

(define_insn ""
  [(set (pc)
        (if_then_else (gtu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

(define_insn ""
  [(set (pc)
        (if_then_else (ltu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

(define_insn ""
  [(set (pc)
        (if_then_else (geu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

(define_insn ""
  [(set (pc)
        (if_then_else (leu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

;; Tablejump 
;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
(define_insn "tablejump"
  [(set (pc)
        (match_operand:QI 0 "register_operand" "b"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jc 15,0,r%0   ; tablejump label_ref=%1")


;; Unconditional jump
(define_insn "jump"
  [(set (pc)
        (label_ref (match_operand 0 "" "")))]
  ""
  "jc 15,%0")

;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
(define_insn "call_value"
  [(set (match_operand 0 "register_operand" "r")
        (call (match_operand:QI 1 "memory_operand" "m")
              (match_operand:QI 2 "general_operand" "g")))]
  ;; Operand 2 not really used for 1750.
  ""
  "sjs r15,%1   ; return value in R0")

;; Call subroutine with no return value.

;;  Operand 1 not really used in MIL-STD-1750.
(define_insn ""
  [(call (match_operand:QI 0 "memory_operand" "mp")
         (match_operand:QI 1 "general_operand" ""))]
  ""
  "sjs r15,%0   ; no return value")

;;;;;;;;;;;; 1750: NOT READY YET.
(define_insn "call"
  [(call (match_operand:QI 0 "" "")
         (match_operand:QI 1 "" ""))]
  ""
  "ANYCALL %0")


; (define_insn "return"
;   [(return)]
;   ""
;   "*
;    { 
;         rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size());
;         output_asm_insn(\"ret.m  %0\",&oprnd);
;         return \"\;\";
;    } ")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
  ""
  "jci 15,%0")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")


;; Subtract One and Jump (if non-zero)
(define_peephole 
  [(set (match_operand:QI 0 "register_operand" "=r")
        (plus:QI (match_operand:QI 1 "register_operand" "%0")
                 (match_operand:QI 2 "immediate_operand" "J")))
   (set (cc0) (match_dup 0))
   (set (pc)
        (if_then_else (ne (cc0) (const_int 0))
         (label_ref (match_operand 3 "" ""))
         (pc)))
   ]
  "INTVAL(operands[2]) == -1"
  "soj r%0,%3")

;; Combine a Load Register with subsequent increment/decrement into a LIM
(define_peephole 
  [(set (match_operand:QI 0 "register_operand" "=r")
        (match_operand:QI 1 "register_operand" "b"))
   (set (match_dup 0)
        (plus:QI (match_dup 0)
                 (match_operand:QI 2 "immediate_operand" "i")))]
  "REGNO(operands[1]) > 0"
  "lim r%0,%2,r%1  ; LR,inc/dec peephole")

;; Eliminate the redundant load in a store/load sequence
(define_peephole 
  [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
			  (match_operand:QI 1 "immediate_operand" "i")))
	(match_operand:QI 2 "register_operand" "r"))
   (set (match_operand:QI 3 "register_operand" "=r")
	(mem:QI (plus:QI (match_dup 0)
			 (match_dup 1))))
   ]
  "REGNO(operands[2]) == REGNO(operands[3])"
  "st r%2,%1,r%0  ; eliminated previous redundant load")

;;;End.