1750a.md

gcc库的原代码,对编程有很大帮助.

;;- Machine description for GNU compiler
;;- MIL-STD-1750A version.
;; Copyright (C) 1994, 1995 Free Software Foundation, Inc.
;; Contributed by O.M.Kellogg, DASA ([e-mail]).

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 1, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;;- instruction definitions

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;- When naming insn's (operand 0 of define_insn) be careful about using
;;- names from other targets machine descriptions.

;; MIL-STD-1750 specific remarks:
;;
;; 1) BITS_PER_UNIT = 16
;;
;; 2) GCC   to    MIL-STD-1750       data type mappings:
;;    QImode => single integer (16 bits or 1 reg).
;;    HImode => double integer (32 bits or 2 regs).
;;    HFmode => single precision float (32 bits or 2 regs).
;;    TQFmode => extended precision float (48 bits or 3 regs).
;; 
;; 3) Immediate integer operands Constraints:
;;    'I'  1 .. 16
;;    'J' -1 ..-16
;;    'K'  0 .. 15
;;    'L'  0 .. 255
;;    'M' -32768 .. 32767
;;    'O' => 0  (for optimizations and GCC quirks)
;;
;; Further notes:
;;-  Assembly output ending in ".M" are macros in file M1750.INC


;; stackpush
(define_insn ""
  [(set (match_operand:QI 0 "push_operand" "=<")
        (match_operand:QI 1 "general_operand" "r"))]
  ""
  "pshm r%1,r%1  ; stackptr = R%0")

(define_insn ""
  [(set (match_operand:HI 0 "push_operand" "=<")
        (match_operand:HI 1 "general_operand" "r"))]
  ""
  "*
   { 
        rtx new_operands[3];
        new_operands[2] = operands[0];
        new_operands[0] = operands[1];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
        output_asm_insn(\"pshm r%0,r%1  ; stackptr = r%2\",new_operands);
        return \";\";
   } ")

(define_insn ""
  [(set (match_operand:HF 0 "push_operand" "=<")
        (match_operand:HF 1 "general_operand" "r"))]
  ""
  "*
  { 
        rtx new_operands[3];
        new_operands[2] = operands[0];
        new_operands[0] = operands[1];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
        output_asm_insn(\"pshm r%0,r%1  ; stackptr = r%2\",new_operands);
        return \";\";
   } ")

(define_insn ""
  [(set (match_operand:TQF 0 "push_operand" "=<")
        (match_operand:TQF 1 "general_operand" "r"))]
  ""
  "*
   { 
        rtx new_operands[3];
        new_operands[2] = operands[0];
        new_operands[0] = operands[1];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2);
        output_asm_insn(\"pshm r%0,r%1  ; stackptr = r%2\",new_operands);
        return \";\";
   } ")

;; stackpop
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=r")
        (match_operand:QI 1 "push_operand" ">"))]
  ""
  "popm r%1,r%1")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=r")
        (match_operand:HI 1 "push_operand" ">"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[0];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
        output_asm_insn(\"popm r%0,r%1\",new_operands);
        return \";\";
   } ")

(define_insn ""
  [(set (match_operand:HF 0 "general_operand" "=r")
        (match_operand:HF 1 "push_operand" ">"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[0];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
        output_asm_insn(\"popm r%0,r%1\",new_operands);
        return \";\";
   } ")

(define_insn ""
  [(set (match_operand:TQF 0 "general_operand" "=r")
        (match_operand:TQF 1 "push_operand" ">"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[0];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2);
        output_asm_insn(\"popm r%0,r%1\",new_operands);
        return \";\";
   } ")

;; Test operations. These shouldn't really occur for 1750:
;; all important instructions set the cc's (see NOTICE_UPDATE_CC)

(define_insn "tstqi"
  [(set (cc0)
        (match_operand:QI 0 "register_operand" "r"))]
  ""
  "lr r%0,r%0   ; from tstqi")

(define_insn "tsthi"
  [(set (cc0)
        (match_operand:HI 0 "register_operand" "r"))]
  ""
  "dlr r%0,r%0   ; from tsthi")

(define_insn "tsthf"
  [(set (cc0)
        (match_operand:HF 0 "register_operand" "r"))]
  ""
  "dlr r%0,r%0   ; from tsthf")

;; This one is happy with "roughly zero" :-)  (should be improved)
(define_insn "tsttqf"
  [(set (cc0)
        (match_operand:TQF 0 "register_operand" "r"))]
  ""
  "dlr r%0,r%0   ; from tsttqf")


;; block move.

; there is a problem with this insn in gcc-2.2.3
; (clobber (match_dup 2)) does not prevent use of this operand later
;
(define_insn "movstrqi"
  [(set (mem:BLK (match_operand:QI 0 "register_operand" "r"))
	(mem:BLK (match_operand:QI 1 "register_operand" "r")))
   (use (match_operand:QI 2 "register_operand" "r"))
   (use (match_operand:QI 3 "immediate_operand" ""))
   (clobber (match_dup 0))
   (clobber (match_dup 1))
   (clobber (match_dup 2))]
  ""
  "* return (char *)movcnt_regno_adjust(operands); ")


;; compare instructions.

(define_insn "cmpqi"
  [(set (cc0)
        (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
                 (match_operand:QI 1 "general_operand"  "I,J,i,r,m")))]
  ""
  "*
   {
     if (next_cc_user_is_unsigned (insn))
       switch (which_alternative)
	 {
	 case 0:
	 case 1:
	 case 2:
	   return \"ucim.m %0,%1\";
	 case 3:
	   return \"ucr.m %0,%1\";
	 case 4:
	   return \"uc.m %0,%1\";
	 }
     else
       switch (which_alternative)
	 {
	 case 0:
	   return \"cisp r%0,%1\";
	 case 1:
	   return \"cisn r%0,%J1\";
	 case 2:
	   return \"cim  r%0,%1\";
	 case 3:
	   return \"cr   r%0,r%1\";
	 case 4:
	   return \"c    r%0,%1\";
	 }
   } ")

(define_insn "cmphi"
  [(set (cc0)
        (compare (match_operand:HI 0 "general_operand" "r,r")
                 (match_operand:HI 1 "general_operand" "r,m")))]
  ""
  "@
    dcr r%0,r%1
    dc  r%0,%1 ")

(define_insn "cmphf"
 [(set (cc0)
       (compare (match_operand:HF 0 "general_operand" "r,z,r")
                (match_operand:HF 1 "general_operand" "r,Q,m")))]
 ""
 "@
   fcr r%0,r%1
   fcb %Q1
   fc  r%0,%1 ")

(define_insn "cmptqf"
  [(set (cc0)
        (compare (match_operand:TQF 0 "general_operand" "r,r")
                 (match_operand:TQF 1 "general_operand" "r,m")))]
  ""
  "@
    efcr r%0,r%1
    efc  r%0,%1 ")


;; truncation instructions
;;- 1750: any needed?

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (truncate:QI
         (match_operand:HI 1 "register_operand" "r")))]
  ""
  "*
     {
	rtx new_operands[2];
	new_operands[0] = operands[0];
	new_operands[1] = gen_rtx (REG, HImode, REGNO(operands[1]) + 1);
        output_asm_insn(\"lr r%0,r%1  ;trunchiqi2\",new_operands);
        return \";\";
     } ")

;; zero extension instructions

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
        (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))]
  ""
  "*
      {
	rtx new_opnds[2];
        output_asm_insn(\"xorr r%0,r%0   ;zero_extendqihi2\",operands);
	new_opnds[0] = gen_rtx (REG, HImode, REGNO(operands[0]) + 1);
	new_opnds[1] = operands[1];
        switch (which_alternative)
          {
            case 0:
              output_asm_insn(\"lr  r%0,r%1\",new_opnds);
              break;
            case 1:
              output_asm_insn(\"l   r%0,%1\",new_opnds);
              break;
            case 2:
              output_asm_insn(\"lim r%0,%1\",new_opnds);
              break;
          }
        return \";\";
      } ")

;; sign extension instructions

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
        (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )]
  ""
  "@
    lr  r%0,r%1 ;extendqihi2\;dsra r%0,16
    l   r%0,%1  ;extendqihi2\;dsra r%0,16
    lim r%0,%1  ;extendqihi2\;dsra r%0,16 ")


;; Conversions between float and double.

; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
(define_insn "extendhftqf2"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
  ""
  "*
      {
	rtx new_opnds[2];
	new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 2);
	new_opnds[1] = operands[1];
        output_asm_insn(\"xorr r%0,r%0   ;extendhftqf2\",new_opnds);
        if (which_alternative == 0)
          return \"dlr r%0,r%1   ; put condition codes back on track\";
        else
          return \"dl  r%0,%1    ; put condition codes back on track\";
      } ")

; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
(define_insn "trunctqfhf2"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (float_truncate:HF
          (match_operand:TQF 1 "general_operand" "r,m")))]
  ""
  "@
     dlr r%0,r%1  ;trunctqfhf2
     dl  r%0,%1   ;trunctqfhf2 ")


;; Conversion between fixed point and floating point.

(define_insn "floatqihf2"
  [(set           (match_operand:HF 0 "register_operand" "=r")
        (float:HF (match_operand:QI 1 "register_operand" "r")))]
  ""
  "flt r%0,r%1")

(define_insn "floathitqf2"
  [(set           (match_operand:TQF 0 "register_operand" "=r")
        (float:TQF (match_operand:HI 1 "register_operand" "r")))]
  ""
  "eflt r%0,r%1")


;; Convert floats to ints

(define_insn "fix_trunchfqi2"
  [(set                 (match_operand:QI 0 "register_operand" "=r")
        (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
  ""
  "fix r%0,r%1")

(define_insn "fix_trunctqfhi2"
  [(set                 (match_operand:HI 0 "register_operand" "=r")
        (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
  ""
  "efix r%0,r%1")


;; Move instructions

;; We can't deal with normal byte-size characters, only with WIDE characters!
;; This may appear as a serious restriction, but it also opens the doors
;; for ISO 10646  :-)

;; 16-bit moves

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,t,r,Q,m,m")
        (match_operand:QI 1 "general_operand"  "O,I,J,M,i,r,Q,m,t,r,K"))]
  ""
  "@
     xorr r%0,r%0
     lisp r%0,%1
     lisn r%0,%J1
     lim  r%0,%1  ; 'M' constraint
     lim  r%0,%1  ; 'i' constraint
     lr   r%0,r%1
     lb   %Q1
     l    r%0,%1
     stb  %Q0
     st   r%1,%0
     stc  %1,%0   ")

;; 32-bit moves

; Set HIreg to constant
(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
        (match_operand:HI 1 "immediate_operand" "i"))]
  ""
  "*
      {
        rtx new_opnds[2];
        int val = INTVAL(operands[1]);
        if (val >= 0)
          {
            if (val <= 65535)
              {
                new_opnds[0] = gen_rtx(REG,QImode,REGNO(operands[0]));
                new_opnds[1] = operands[1];
                output_asm_insn(\"xorr   r%0,r%0 ;movhi cst->reg\",new_opnds);
                REGNO(new_opnds[0]) += 1;
                if (val == 0)
                  output_asm_insn(\"xorr r%0,r%0\",new_opnds);
                else if (val <= 16)
                  output_asm_insn(\"lisp r%0,%1\",new_opnds);
                else
                  output_asm_insn(\"lim  r%0,%1\",new_opnds);
                return \";\";
              }
          }
        else if (val >= -16)
          return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\";
	new_opnds[0] = gen_rtx(REG, QImode, REGNO(operands[0]));
	new_opnds[1] = gen_rtx(CONST_INT,VOIDmode,(INTVAL(operands[1])) >> 16);
        output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",new_opnds);
        INTVAL(new_opnds[1]) = val & 0xFFFF;
        REGNO(new_opnds[0]) += 1;
        output_asm_insn(\"lim r%0,%1\",new_opnds);
        return \";\";
      }
  ")

(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=r,z,r,Q,m")
        (match_operand:HI 1 "general_operand"  "r,Q,m,z,r"))]
  ""
  "@
    dlr  r%0,r%1
    dlb  %Q1
    dl   r%0,%1
    dstb %Q0
    dst  r%1,%0 ")


;; Single-Float moves are *same* as HImode moves:

;(define_insn "movhf"
;  [(set (match_operand:HF 0 "general_operand" "=r,r,r,m")
;        (match_operand:HF 1 "general_operand"  "F,r,m,r"))]
;  ""
;  "@
;    %D1\;dl r%0,%F1
;    dlr r%0,r%1
;    dl  r%0,%1
;    dst r%1,%0 ")

(define_insn "movhf"
  [(set (match_operand:HF 0 "general_operand" "=r,z,r,Q,m")
        (match_operand:HF 1 "general_operand"  "r,Q,m,z,r"))]
  ""
  "@
    dlr  r%0,r%1
    dlb  %Q1
    dl   r%0,%1
    dstb %Q0
    dst  r%1,%0 ")


;; Longfloat moves

;(define_insn "movtqf"
;  [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
;        (match_operand:TQF 1 "general_operand"  "F,r,m,r"))]