📄 clock10.rpt
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# _LC1_D5 & !_LC1_D12 & _LC3_D5;
-- Node name is '|clock2:21|74162:3|:46' = '|clock2:21|74162:3|QD'
-- Equation name is '_LC1_D3', type is buried
_LC1_D3 = DFFE( _EQ023, _LC2_D15, VCC, VCC, VCC);
_EQ023 = _LC1_D3 & _LC1_D12 & !_LC2_D7
# _LC1_D3 & _LC1_D12 & _LC1_D16;
-- Node name is '|clock2:21|74162:3|~33~1'
-- Equation name is '_LC3_D5', type is buried
-- synthesized logic cell
_LC3_D5 = LCELL( _EQ024);
_EQ024 = _LC1_D12 & !_LC1_D16 & _LC2_D7;
-- Node name is '|clock2:21|74162:3|~74~1'
-- Equation name is '_LC1_D16', type is buried
-- synthesized logic cell
!_LC1_D16 = _LC1_D16~NOT;
_LC1_D16~NOT = LCELL( _EQ025);
_EQ025 = _LC1_D7 & !_LC2_D31 & !_LC4_F33
# _LC1_D7 & !_LC2_D31 & !s;
-- Node name is '|clock4gdf:67|:36'
-- Equation name is '_LC7_F2', type is buried
_LC7_F2 = LCELL( _EQ026);
_EQ026 = _LC1_D12
# !_LC4_F2
# !_LC3_F2
# _LC4_F33;
-- Node name is '|clock4gdf:67|74162:1|:43' = '|clock4gdf:67|74162:1|QA'
-- Equation name is '_LC1_F2', type is buried
_LC1_F2 = DFFE( _EQ027, _LC2_D13, VCC, VCC, VCC);
_EQ027 = !_LC1_F2 & _LC3_B6 & _LC7_F2
# _LC1_F2 & !_LC3_B6 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:1|:44' = '|clock4gdf:67|74162:1|QB'
-- Equation name is '_LC8_F2', type is buried
_LC8_F2 = DFFE( _EQ028, _LC2_D13, VCC, VCC, VCC);
_EQ028 = _LC2_F2 & _LC3_B6 & _LC7_F2 & !_LC8_F2
# !_LC3_B6 & _LC7_F2 & _LC8_F2
# !_LC2_F2 & _LC7_F2 & _LC8_F2;
-- Node name is '|clock4gdf:67|74162:1|:45' = '|clock4gdf:67|74162:1|QC'
-- Equation name is '_LC6_F1', type is buried
_LC6_F1 = DFFE( _EQ029, _LC2_D13, VCC, VCC, VCC);
_EQ029 = _LC1_F1 & !_LC6_F1
# _LC1_F1 & !_LC7_F2
# !_LC1_F1 & _LC6_F1 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:1|:46' = '|clock4gdf:67|74162:1|QD'
-- Equation name is '_LC4_F1', type is buried
_LC4_F1 = DFFE( _EQ030, _LC2_D13, VCC, VCC, VCC);
_EQ030 = _LC5_F1 & !_LC6_F1
# !_LC1_F1 & _LC5_F1
# _LC1_F1 & !_LC5_F1 & _LC6_F1;
-- Node name is '|clock4gdf:67|74162:1|:30'
-- Equation name is '_LC3_F2', type is buried
!_LC3_F2 = _LC3_F2~NOT;
_LC3_F2~NOT = LCELL( _EQ031);
_EQ031 = !_LC8_F2
# !_LC1_F2;
-- Node name is '|clock4gdf:67|74162:1|:33'
-- Equation name is '_LC1_F1', type is buried
_LC1_F1 = LCELL( _EQ032);
_EQ032 = _LC1_F2 & _LC3_B6 & _LC7_F2 & _LC8_F2;
-- Node name is '|clock4gdf:67|74162:1|~54~1'
-- Equation name is '_LC2_F2', type is buried
-- synthesized logic cell
_LC2_F2 = LCELL( _EQ033);
_EQ033 = _LC1_F2 & !_LC4_F1;
-- Node name is '|clock4gdf:67|74162:1|:55'
-- Equation name is '_LC5_F1', type is buried
_LC5_F1 = LCELL( _EQ034);
_EQ034 = !_LC1_F2 & _LC4_F1 & _LC7_F2
# !_LC3_B6 & _LC4_F1 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:3|:43' = '|clock4gdf:67|74162:3|QA'
-- Equation name is '_LC2_F1', type is buried
_LC2_F1 = DFFE( _EQ035, _LC2_D13, VCC, VCC, VCC);
_EQ035 = !_LC2_F1 & _LC3_F1
# _LC3_F1 & !_LC7_F2
# _LC2_F1 & !_LC3_F1 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:3|:44' = '|clock4gdf:67|74162:3|QB'
-- Equation name is '_LC4_F2', type is buried
_LC4_F2 = DFFE( _EQ036, _LC2_D13, VCC, VCC, VCC);
_EQ036 = _LC2_E4 & !_LC4_E4 & !_LC4_F2
# _LC2_E4 & !_LC4_E4 & !_LC7_F2
# _LC4_E4 & _LC4_F2 & _LC7_F2
# !_LC2_E4 & _LC4_F2 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:3|:45' = '|clock4gdf:67|74162:3|QC'
-- Equation name is '_LC7_E4', type is buried
_LC7_E4 = DFFE( _EQ037, _LC2_D13, VCC, VCC, VCC);
_EQ037 = _LC2_E4 & _LC4_F2 & !_LC7_E4
# _LC2_E4 & _LC4_F2 & !_LC7_F2
# !_LC4_F2 & _LC7_E4 & _LC7_F2
# !_LC2_E4 & _LC7_E4 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:3|:46' = '|clock4gdf:67|74162:3|QD'
-- Equation name is '_LC4_E4', type is buried
_LC4_E4 = DFFE( _EQ038, _LC2_D13, VCC, VCC, VCC);
_EQ038 = _LC1_E4 & !_LC7_F1
# _LC1_E4 & !_LC4_E4
# _LC1_E4 & !_LC7_F2
# !_LC1_E4 & _LC4_E4 & _LC7_F1 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:3|~54~1'
-- Equation name is '_LC2_E4', type is buried
-- synthesized logic cell
_LC2_E4 = LCELL( _EQ039);
_EQ039 = _LC2_F1 & _LC3_F1;
-- Node name is '|clock4gdf:67|74162:3|:57'
-- Equation name is '_LC1_E4', type is buried
_LC1_E4 = LCELL( _EQ040);
_EQ040 = _LC2_F1 & _LC3_F1 & _LC4_F2 & _LC7_E4;
-- Node name is '|clock4gdf:67|74162:3|:59'
-- Equation name is '_LC3_F1', type is buried
_LC3_F1 = LCELL( _EQ041);
_EQ041 = _LC1_F2 & _LC3_B6 & _LC4_F1 & _LC7_F2;
-- Node name is '|clock4gdf:67|74162:3|:74'
-- Equation name is '_LC7_F1', type is buried
_LC7_F1 = LCELL( _EQ042);
_EQ042 = !_LC1_F2
# !_LC3_B6
# !_LC4_F1
# !_LC2_F1;
-- Node name is '|clock8:58|21mux:4|:5' = '|clock8:58|21mux:4|Y'
-- Equation name is '_LC3_B6', type is buried
!_LC3_B6 = _LC3_B6~NOT;
_LC3_B6~NOT = LCELL( _EQ043);
_EQ043 = _LC1_D12 & s;
-- Node name is '|clock8:58|21mux:5|:5' = '|clock8:58|21mux:5|Y'
-- Equation name is '_LC3_D3', type is buried
_LC3_D3 = LCELL( _EQ044);
_EQ044 = clk & s
# b3 & !s;
-- Node name is '|clock8:58|21mux:6|:5' = '|clock8:58|21mux:6|Y'
-- Equation name is '_LC2_D15', type is buried
_LC2_D15 = LCELL( _EQ045);
_EQ045 = clk & s
# b2 & !s;
-- Node name is '|clock8:58|21mux:7|:5' = '|clock8:58|21mux:7|Y'
-- Equation name is '_LC2_D13', type is buried
_LC2_D13 = LCELL( _EQ046);
_EQ046 = b1 & !s
# clk & s;
-- Node name is ':45'
-- Equation name is '_LC6_D3', type is buried
_LC6_D3 = DFFE(!_LC6_D3, _LC3_D3, VCC, VCC, VCC);
-- Node name is ':51'
-- Equation name is '_LC1_D14', type is buried
_LC1_D14 = DFFE(!_LC1_D14, _LC2_D15, VCC, VCC, VCC);
Project Information d:\wu\clock10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,884K
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