📄 clock10.rpt
字号:
Total input I/O cell registers required: 0
Total output pins required: 27
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 49
Total flipflops required: 26
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 3 0 3 0 3 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 18/0
E: 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/0
F: 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 5 0 26/0
Total: 7 6 3 4 3 1 3 0 1 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 7 0 5 0 49/0
Device-Specific Information: d:\wu\clock10.rpt
clock10
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
18 - - C -- INPUT ^ 0 0 0 1 b1
12 - - C -- INPUT ^ 0 0 0 1 b2
8 - - A -- INPUT ^ 0 0 0 1 b3
126 - - - -- INPUT ^ 0 0 0 3 clk
19 - - D -- INPUT ^ 0 0 0 8 s
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\wu\clock10.rpt
clock10
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - F -- OUTPUT 0 1 0 0 g0
31 - - F -- OUTPUT 0 1 0 0 g1
32 - - F -- OUTPUT 0 1 0 0 g2
33 - - F -- OUTPUT 0 1 0 0 g3
73 - - - 01 OUTPUT 0 1 0 0 h0
78 - - F -- OUTPUT 0 1 0 0 h1
79 - - F -- OUTPUT 0 1 0 0 h2
80 - - F -- OUTPUT 0 1 0 0 h3
68 - - - 07 OUTPUT 0 1 0 0 i0
69 - - - 06 OUTPUT 0 1 0 0 i1
70 - - - 05 OUTPUT 0 1 0 0 i2
72 - - - 03 OUTPUT 0 1 0 0 i3
89 - - D -- OUTPUT 0 1 0 0 light0
92 - - D -- OUTPUT 0 1 0 0 light1
41 - - - 31 OUTPUT 0 1 0 0 m0
42 - - - 28 OUTPUT 0 1 0 0 m1
65 - - - 09 OUTPUT 0 1 0 0 m2
67 - - - 08 OUTPUT 0 1 0 0 m3
81 - - F -- OUTPUT 0 1 0 0 r0
82 - - F -- OUTPUT 0 1 0 0 r1
83 - - E -- OUTPUT 0 1 0 0 r2
86 - - E -- OUTPUT 0 1 0 0 r3
99 - - B -- OUTPUT 0 1 0 0 sp
36 - - - 36 OUTPUT 0 1 0 0 s0
37 - - - 35 OUTPUT 0 1 0 0 s1
38 - - - 34 OUTPUT 0 1 0 0 s2
39 - - - 33 OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\wu\clock10.rpt
clock10
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - F 33 AND2 ! 0 4 0 10 |clock1:24|:22
- 1 - F 19 DFFE 0 1 1 6 |clock1:24|74162:1|QA (|clock1:24|74162:1|:43)
- 3 - F 33 DFFE 0 3 1 2 |clock1:24|74162:1|QB (|clock1:24|74162:1|:44)
- 5 - F 33 DFFE 0 3 1 1 |clock1:24|74162:1|QC (|clock1:24|74162:1|:45)
- 7 - F 33 DFFE 0 4 1 4 |clock1:24|74162:1|QD (|clock1:24|74162:1|:46)
- 3 - F 35 AND2 0 3 0 2 |clock1:24|74162:3|:33
- 2 - F 35 DFFE 0 3 1 4 |clock1:24|74162:3|QA (|clock1:24|74162:3|:43)
- 1 - F 35 DFFE 0 4 1 1 |clock1:24|74162:3|QB (|clock1:24|74162:3|:44)
- 2 - F 33 DFFE 0 3 1 2 |clock1:24|74162:3|QC (|clock1:24|74162:3|:45)
- 1 - F 33 DFFE 0 4 1 1 |clock1:24|74162:3|QD (|clock1:24|74162:3|:46)
- 5 - F 35 AND2 s 0 2 0 1 |clock1:24|74162:3|~54~1
- 6 - F 33 OR2 s 0 4 0 1 |clock1:24|74162:3|~55~1
- 4 - F 35 AND2 0 3 0 3 |clock1:24|74162:3|:59
- 1 - D 12 OR2 0 4 0 7 |clock2:21|:22
- 3 - D 07 OR2 1 3 0 2 |clock2:21|74162:1|:33
- 1 - D 31 DFFE 1 2 1 2 |clock2:21|74162:1|QA (|clock2:21|74162:1|:43)
- 2 - D 27 DFFE 0 3 1 1 |clock2:21|74162:1|QB (|clock2:21|74162:1|:44)
- 1 - D 09 DFFE 0 2 1 1 |clock2:21|74162:1|QC (|clock2:21|74162:1|:45)
- 1 - D 07 DFFE 0 4 1 3 |clock2:21|74162:1|QD (|clock2:21|74162:1|:46)
- 2 - D 31 OR2 ! 1 2 0 4 |clock2:21|74162:1|:74
- 3 - D 05 AND2 s 0 3 0 2 |clock2:21|74162:3|~33~1
- 2 - D 07 DFFE 0 3 1 3 |clock2:21|74162:3|QA (|clock2:21|74162:3|:43)
- 1 - D 05 DFFE 0 4 1 1 |clock2:21|74162:3|QB (|clock2:21|74162:3|:44)
- 2 - D 05 DFFE 0 4 1 1 |clock2:21|74162:3|QC (|clock2:21|74162:3|:45)
- 1 - D 03 DFFE 0 4 1 1 |clock2:21|74162:3|QD (|clock2:21|74162:3|:46)
- 1 - D 16 OR2 s ! 1 3 0 3 |clock2:21|74162:3|~74~1
- 7 - F 02 OR2 0 4 0 10 |clock4gdf:67|:36
- 3 - F 02 OR2 ! 0 2 0 1 |clock4gdf:67|74162:1|:30
- 1 - F 01 AND2 0 4 0 2 |clock4gdf:67|74162:1|:33
- 1 - F 02 DFFE 0 3 1 6 |clock4gdf:67|74162:1|QA (|clock4gdf:67|74162:1|:43)
- 8 - F 02 DFFE 0 4 1 2 |clock4gdf:67|74162:1|QB (|clock4gdf:67|74162:1|:44)
- 6 - F 01 DFFE 0 3 1 1 |clock4gdf:67|74162:1|QC (|clock4gdf:67|74162:1|:45)
- 4 - F 01 DFFE 0 4 1 4 |clock4gdf:67|74162:1|QD (|clock4gdf:67|74162:1|:46)
- 2 - F 02 AND2 s 0 2 0 1 |clock4gdf:67|74162:1|~54~1
- 5 - F 01 OR2 0 4 0 1 |clock4gdf:67|74162:1|:55
- 2 - F 01 DFFE 0 3 1 3 |clock4gdf:67|74162:3|QA (|clock4gdf:67|74162:3|:43)
- 4 - F 02 DFFE 0 4 1 3 |clock4gdf:67|74162:3|QB (|clock4gdf:67|74162:3|:44)
- 7 - E 04 DFFE 0 4 1 1 |clock4gdf:67|74162:3|QC (|clock4gdf:67|74162:3|:45)
- 4 - E 04 DFFE 0 4 1 1 |clock4gdf:67|74162:3|QD (|clock4gdf:67|74162:3|:46)
- 2 - E 04 AND2 s 0 2 0 2 |clock4gdf:67|74162:3|~54~1
- 1 - E 04 AND2 0 4 0 1 |clock4gdf:67|74162:3|:57
- 3 - F 01 AND2 0 4 0 3 |clock4gdf:67|74162:3|:59
- 7 - F 01 OR2 0 4 0 1 |clock4gdf:67|74162:3|:74
- 3 - B 06 AND2 ! 1 1 1 6 |clock8:58|21mux:4|Y (|clock8:58|21mux:4|:5)
- 3 - D 03 OR2 3 0 0 9 |clock8:58|21mux:5|Y (|clock8:58|21mux:5|:5)
- 2 - D 15 OR2 3 0 0 9 |clock8:58|21mux:6|Y (|clock8:58|21mux:6|:5)
- 2 - D 13 OR2 3 0 0 8 |clock8:58|21mux:7|Y (|clock8:58|21mux:7|:5)
- 6 - D 03 DFFE 0 1 1 0 :45
- 1 - D 14 DFFE 0 1 1 0 :51
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\wu\clock10.rpt
clock10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
D: 7/144( 4%) 12/ 72( 16%) 0/ 72( 0%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 8/ 72( 11%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
F: 2/144( 1%) 12/ 72( 16%) 7/ 72( 9%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\wu\clock10.rpt
clock10
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 9 |clock8:58|21mux:5|Y
LCELL 9 |clock8:58|21mux:6|Y
LCELL 8 |clock8:58|21mux:7|Y
Device-Specific Information: d:\wu\clock10.rpt
clock10
** EQUATIONS **
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
clk : INPUT;
s : INPUT;
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