📄 clock1.rpt
字号:
- 1 - A 01 DFFE + 0 3 1 3 |74162:3|QA (|74162:3|:43)
- 7 - A 01 DFFE + 0 3 1 1 |74162:3|QB (|74162:3|:44)
- 5 - A 01 DFFE + 0 3 1 1 |74162:3|QC (|74162:3|:45)
- 8 - A 01 DFFE + 0 3 1 1 |74162:3|QD (|74162:3|:46)
- 3 - A 01 AND2 s 0 4 0 2 |74162:3|~54~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\sz\clock1.rpt
clock1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\sz\clock1.rpt
clock1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\sz\clock1.rpt
clock1
** EQUATIONS **
clk : INPUT;
-- Node name is 'cr'
-- Equation name is 'cr', type is output
cr = !_LC2_A1;
-- Node name is 'g0'
-- Equation name is 'g0', type is output
g0 = _LC1_A3;
-- Node name is 'g1'
-- Equation name is 'g1', type is output
g1 = _LC2_A2;
-- Node name is 'g2'
-- Equation name is 'g2', type is output
g2 = _LC1_A2;
-- Node name is 'g3'
-- Equation name is 'g3', type is output
g3 = _LC6_A2;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC1_A1;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC7_A1;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC5_A1;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC8_A1;
-- Node name is '|74162:1|:43' = '|74162:1|QA'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = DFFE(!_LC1_A3, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|74162:1|:44' = '|74162:1|QB'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC1_A3 & _LC2_A2
# _LC2_A2 & _LC6_A2
# _LC1_A3 & !_LC2_A2 & !_LC6_A2;
-- Node name is '|74162:1|:45' = '|74162:1|QC'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC1_A2 & !_LC1_A3
# _LC1_A2 & !_LC2_A2
# !_LC1_A2 & _LC1_A3 & _LC2_A2;
-- Node name is '|74162:1|:46' = '|74162:1|QD'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_A3 & _LC6_A2
# _LC1_A2 & _LC1_A3 & _LC2_A2;
-- Node name is '|74162:3|:43' = '|74162:3|QA'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_A1 & _LC1_A3 & _LC2_A1 & _LC6_A2
# _LC1_A1 & !_LC1_A3 & _LC2_A1
# _LC1_A1 & _LC2_A1 & !_LC6_A2;
-- Node name is '|74162:3|:44' = '|74162:3|QB'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC3_A1 & !_LC7_A1 & !_LC8_A1
# !_LC2_A1 & _LC3_A1 & !_LC8_A1
# _LC2_A1 & _LC7_A1 & _LC8_A1
# _LC2_A1 & !_LC3_A1 & _LC7_A1;
-- Node name is '|74162:3|:45' = '|74162:3|QC'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC3_A1 & !_LC5_A1 & _LC7_A1
# !_LC2_A1 & _LC3_A1 & _LC7_A1
# _LC2_A1 & _LC5_A1 & !_LC7_A1
# _LC2_A1 & !_LC3_A1 & _LC5_A1;
-- Node name is '|74162:3|:46' = '|74162:3|QD'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC1_A3 & _LC8_A1
# !_LC6_A2 & _LC8_A1
# !_LC1_A1 & _LC8_A1;
-- Node name is '|74162:3|~54~1'
-- Equation name is '_LC3_A1', type is buried
-- synthesized logic cell
_LC3_A1 = LCELL( _EQ008);
_EQ008 = _LC1_A1 & _LC1_A3 & _LC2_A1 & _LC6_A2;
-- Node name is ':22'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ009);
_EQ009 = !_LC5_A1
# !_LC1_A1
# !_LC1_A3
# !_LC6_A2;
Project Information d:\sz\clock1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 33,110K
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