netstart.h

~{WwU_J9SC5D~}ucos~{T4Bk#,1`RkA4=S5wJT>y?IRT#,4x~}uart~{2bJT~}

#ifndef NETSTART_H
#define NETSTART_H

/*
* #define CBUILDER_TEST
*/

#define MHz					1000000
#define fMCLK				50*MHz       
#define MCLK2				(fMCLK/2)

/*
* This is the number of timer ticks that occur per second.
*/
#define TICKS_PER_SECOND	200


/*
* Number of ticks for one second
*/
#define ONE_SECOND			1000    /* In case of time unit[ms] */


#define S8		signed char
#define S16		signed short
#define S32		signed long
#define U8		unsigned char
#define U16		unsigned short
#define U32		unsigned long
#define REG8	volatile unsigned char
#define REG16	volatile unsigned short
#define REG32	volatile unsigned long
#define BYTE	U8

typedef char int8;              /*  1                   1   */
typedef unsigned char uint8;    /*  1                   1   */
typedef short int int16;        /*  2                   2   */
typedef unsigned short uint16;  /*  2                   2   */
typedef long int int32;         /*  4                   4   */
typedef unsigned long uint32;   /*  4                   4   */


/*
* generic names for size types
*/
typedef signed char schar;      /*  1                   1   */
typedef unsigned char uchar;    /*  1                   1   */
typedef short int sshort;       /*  2                   2   */
#ifndef _STDIO_H_
#ifndef _STRING_H_
typedef unsigned short ushort;  /*  2                   2   */
typedef unsigned int uint;      /*  2                   2   */
#endif
#endif
typedef short sint;             /*  2                   2   */
typedef long int slint;         /*  4                   4   */
typedef long int slong;         /*  4                   4   */
typedef unsigned long ulint;    /*  4                   4   */
typedef unsigned long ulong;    /*  4                   4   */
typedef short std_Boolean;


#define BD_LAN_STOP		{}
#define DEBUG			1        /* DEBUG mode */

/*
* ASIC Address Definition
*/
#define VPint    *(volatile unsigned int *)
#define VPshort  *(volatile unsigned short *)
#define VPchar   *(volatile unsigned char *)


/*
* Special Register Start Address After System Reset
*/
#ifdef CBUILDER_TEST

extern char ArrayAddr[];
#define _SPSTR_RESET	(VPint(0x1000000))
#define Base_Addr		ArrayAddr
#define INTADDR			(Reset_Addr+0x20)
#define SPSTR			(VPint(Base_Addr))

#else  /* CBUILDER_TEST */

#define _SPSTR_RESET	(VPint(0x1000000))
#define Base_Addr		0x3ff0000
#define INTADDR			(Reset_Addr+0x20)
#define SPSTR			(VPint(Base_Addr))

#endif  /* ifdef CBUILDER_TEST */


/*
* System Manager Register
*/
#define SYSCFG			(VPint(Base_Addr+0x0000))

#define CLKCON			(VPint(Base_Addr+0x3000))
#define EXTACON0		(VPint(Base_Addr+0x3008))
#define EXTACON1		(VPint(Base_Addr+0x300c))
#define EXTDBWTH		(VPint(Base_Addr+0x3010))
#define ROMCON0			(VPint(Base_Addr+0x3014))
#define ROMCON1			(VPint(Base_Addr+0x3018))
#define ROMCON2			(VPint(Base_Addr+0x301c))
#define ROMCON3			(VPint(Base_Addr+0x3020))
#define ROMCON4			(VPint(Base_Addr+0x3024))
#define ROMCON5			(VPint(Base_Addr+0x3028))
#define DRAMCON0		(VPint(Base_Addr+0x302c))
#define DRAMCON1		(VPint(Base_Addr+0x3030))
#define DRAMCON2		(VPint(Base_Addr+0x3034))
#define DRAMCON3		(VPint(Base_Addr+0x3038))
#define REFEXTCON		(VPint(Base_Addr+0x303c))


/*
* Ethernet BDMA Register
*/
#define BDMATXCON		(VPint(Base_Addr+0x9000))
#define BDMARXCON		(VPint(Base_Addr+0x9004))
#define BDMATXPTR		(VPint(Base_Addr+0x9008))
#define BDMARXPTR		(VPint(Base_Addr+0x900c))
#define BDMARXLSZ		(VPint(Base_Addr+0x9010))
#define BDMASTAT		(VPint(Base_Addr+0x9014))

/*
* Content Address Memory
*/
#define CAM_BaseAddr	(Base_Addr + 0x9100)
#define CAM_BASE		(VPint(Base_Addr+0x9100))
#define CAM_Reg(x)		(VPint(CAM_BaseAddr+(x*0x4)))

#define BDMATXBUF		(VPint(Base_Addr+0x9200))
#define BDMARXBUF		(VPint(Base_Addr+0x9800))


/*
* Ethernet MAC Register
*/
#define MACCON			(VPint(Base_Addr+0xa000))
#define CAMCON			(VPint(Base_Addr+0xa004))
#define MACTXCON		(VPint(Base_Addr+0xa008))
#define MACTXSTAT		(VPint(Base_Addr+0xa00c))
#define MACRXCON		(VPint(Base_Addr+0xa010))
#define MACRXSTAT		(VPint(Base_Addr+0xa014))
#define STADATA			(VPint(Base_Addr+0xa018))
#define STACON			(VPint(Base_Addr+0xa01c))
#define CAMEN			(VPint(Base_Addr+0xa028))
#define EMISSCNT		(VPint(Base_Addr+0xa03c))
#define EPZCNT			(VPint(Base_Addr+0xa040))
#define ERMPZCNT		(VPint(Base_Addr+0xa044))
#define ETXSTAT			(VPint(Base_Addr+0x9040))
#define MACRXDESTR		(VPint(Base_Addr+0xa064))
#define MACRXSTATEM		(VPint(Base_Addr+0xa090))
#define MACRXFIFO		(VPint(Base_Addr+0xa200))


#ifdef KS32C50100
/*
* KS32C50100 : HDLC Channel A
*/
#define HMODEA			(VPint(Base_Addr+0x7000))
#define HCONA			(VPint(Base_Addr+0x7004))
#define HSTATA			(VPint(Base_Addr+0x7008))
#define HINTENA			(VPint(Base_Addr+0x700c))
#define HTXFIFOCA		(VPint(Base_Addr+0x7010))
#define HTXFIFOTA		(VPint(Base_Addr+0x7014))
#define HRXFIFOA		(VPint(Base_Addr+0x7018))
#define HBRGTCA			(VPint(Base_Addr+0x701c))
#define HPRMBA			(VPint(Base_Addr+0x7020))
#define HSAR0A			(VPint(Base_Addr+0x7024))
#define HSAR1A			(VPint(Base_Addr+0x7028))
#define HSAR2A			(VPint(Base_Addr+0x702c))
#define HSAR3A			(VPint(Base_Addr+0x7030))
#define HMASKA			(VPint(Base_Addr+0x7034))
#define HDMATXPTRA		(VPint(Base_Addr+0x7038))
#define HDMARXPTRA		(VPint(Base_Addr+0x703c))
#define HMFLRA			(VPint(Base_Addr+0x7040))
#define HRBSRA			(VPint(Base_Addr+0x7044))
#define HDLCBaseAddr	(Base_Addr+0x7000)
	
/*
* KS32C50100 : HDLC Channel B
*/
#define HMODEB			(VPint(Base_Addr+0x8000))
#define HCONB			(VPint(Base_Addr+0x8004))
#define HSTATB			(VPint(Base_Addr+0x8008))
#define HINTENB			(VPint(Base_Addr+0x800c))
#define HTXFIFOCB		(VPint(Base_Addr+0x8010))
#define HTXFIFOTB		(VPint(Base_Addr+0x8014))
#define HRXFIFOB		(VPint(Base_Addr+0x8018))
#define HBRGTCB			(VPint(Base_Addr+0x801c))
#define HPRMBB			(VPint(Base_Addr+0x8020))
#define HSAR0B			(VPint(Base_Addr+0x8024))
#define HSAR1B			(VPint(Base_Addr+0x8028))
#define HSAR2B			(VPint(Base_Addr+0x802c))
#define HSAR3B			(VPint(Base_Addr+0x8030))
#define HMASKB			(VPint(Base_Addr+0x8034))
#define HDMATXPTRB		(VPint(Base_Addr+0x8038))
#define HDMARXPTRB		(VPint(Base_Addr+0x803c))
#define HMFLRB			(VPint(Base_Addr+0x8040))
#define HRBSRB			(VPint(Base_Addr+0x8044))

#else
/*
* KS32C5000A : HDLC Channel A
*/
#define HCON0A			(VPint(Base_Addr+0x7000))
#define HCON1A			(VPint(Base_Addr+0x7004))
#define HSTATA			(VPint(Base_Addr+0x7008))
#define HINTENA			(VPint(Base_Addr+0x700c))
#define HTXFIFOCA		(VPint(Base_Addr+0x7010))
#define HTXFIFOTA		(VPint(Base_Addr+0x7014))
#define HRXFIFOA		(VPint(Base_Addr+0x7018))
#define HSADRA			(VPint(Base_Addr+0x701c))
#define HBRGTCA			(VPint(Base_Addr+0x7020))
#define HPRMBA			(VPint(Base_Addr+0x7024))
#define HDMATXMAA		(VPint(Base_Addr+0x7028))
#define HDMARXMAA		(VPint(Base_Addr+0x702c))
#define HDMATXCNTA		(VPint(Base_Addr+0x7030))
#define HDMARXCNTA		(VPint(Base_Addr+0x7034))
#define HDMARXBCNTA		(VPint(Base_Addr+0x7038))

/*
* KS32C5000A : HDLC Channel B
*/
#define HCON0B			(VPint(Base_Addr+0x8000))
#define HCON1B			(VPint(Base_Addr+0x8004))
#define HSTATB			(VPint(Base_Addr+0x8008))
#define HINTENB			(VPint(Base_Addr+0x800c))
#define HTXFIFOCB		(VPint(Base_Addr+0x8010))
#define HTXFIFOTB		(VPint(Base_Addr+0x8014))
#define HRXFIFOB		(VPint(Base_Addr+0x8018))
#define HSADRB			(VPint(Base_Addr+0x801c))
#define HBRGTCB			(VPint(Base_Addr+0x8020))
#define HPRMBB			(VPint(Base_Addr+0x8024))
#define HDMATXMAB		(VPint(Base_Addr+0x8028))
#define HDMARXMAB		(VPint(Base_Addr+0x802c))
#define HDMATXCNTB		(VPint(Base_Addr+0x8030))
#define HDMARXCNTB		(VPint(Base_Addr+0x8034))
#define HDMARXBCNTB		(VPint(Base_Addr+0x8038))

#endif /* ifdef KS32C50100 */


/*
* I2C Bus Register
*/
#define IICCON			(VPint(Base_Addr+0xf000))
#define IICBUF			(VPint(Base_Addr+0xf004))
#define IICPS			(VPint(Base_Addr+0xf008))
#define IICCOUNT		(VPint(Base_Addr+0xf00c))


/*
* GDMA 0
*/
#define GDMACON0			(VPint(Base_Addr+0xb000))
#define GDMA0_RUN_ENABLE	(VPint(Base_Addr+0xb020))
#define GDMASRC0			(VPint(Base_Addr+0xb004))
#define GDMADST0			(VPint(Base_Addr+0xb008))
#define GDMACNT0			(VPint(Base_Addr+0xb00c))


/*
* GDMA 1
*/
#define GDMACON1			(VPint(Base_Addr+0xc000))
#define GDMA1_RUN_ENABLE	(VPint(Base_Addr+0xc020))
#define GDMASRC1			(VPint(Base_Addr+0xc004))
#define GDMADST1			(VPint(Base_Addr+0xc008))
#define GDMACNT1			(VPint(Base_Addr+0xc00c))


/*
* UART 0
*/
#define UARTLCON0		(VPint(Base_Addr+0xd000))
#define UARTCONT0		(VPint(Base_Addr+0xd004))
#define UARTSTAT0		(VPint(Base_Addr+0xd008))
#define UARTTXH0		(VPint(Base_Addr+0xd00c))
#define UARTRXB0		(VPint(Base_Addr+0xd010))
#define UARTBRD0		(VPint(Base_Addr+0xd014))


/*
* UART 1
*/
#define UARTLCON1		(VPint(Base_Addr+0xe000))
#define UARTCONT1		(VPint(Base_Addr+0xe004))
#define UARTSTAT1		(VPint(Base_Addr+0xe008))
#define UARTTXH1		(VPint(Base_Addr+0xe00c))
#define UARTRXB1		(VPint(Base_Addr+0xe010))
#define UARTBRD1		(VPint(Base_Addr+0xe014))


/*
* Timer Register
*/
#define TMOD			(VPint(Base_Addr+0x6000))
#define TDATA0			(VPint(Base_Addr+0x6004))
#define TDATA1			(VPint(Base_Addr+0x6008))
#define TCNT0			(VPint(Base_Addr+0x600c))
#define TCNT1			(VPint(Base_Addr+0x6010))


/*
* I/O Port Interface
*/
#define IOPMOD			(VPint(Base_Addr+0x5000))
#define IOPCON			(VPint(Base_Addr+0x5004))
#define IOPDATA			(VPint(Base_Addr+0x5008))


/*
* Interrupt Controller Register
*/
#define INTMODE			(VPint(Base_Addr+0x4000))
#define INTPEND			(VPint(Base_Addr+0x4004))
#define INTMASK			(VPint(Base_Addr+0x4008))

#define INTPRI0			(VPint(Base_Addr+0x400c))
#define INTPRI1			(VPint(Base_Addr+0x4010))
#define INTPRI2			(VPint(Base_Addr+0x4014))
#define INTPRI3			(VPint(Base_Addr+0x4018))
#define INTPRI4			(VPint(Base_Addr+0x401c))
#define INTPRI5			(VPint(Base_Addr+0x4020))
#define INTOFFSET		(VPint(Base_Addr+0x4024))
#define INTPNDPRI		(VPint(Base_Addr+0x4028))
#define INTPNDTST		(VPint(Base_Addr+0x402C))


/*
* Enable HDLC Interrupt for DISI
*/
#define BD_ALLOW_INTERRUPTS		INTMASK &= ~(1<<(0xc000))
#define BD_DISALLOW_INTERRUPTS	INTMASK |=  (1<<(0xc000))


#endif /* NETSTART_H */