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/* 0x2=3Cycle, 0x3=4Cycle */
.EQU rTacc5, (0x4<<4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.EQU rROMCON5, ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
.EQU rROMCON5_S, ROMEndPtr5_S+ROMBasePtr5_S+rTacc5+rTpa5+PMC5
/*------------------------------------------------------------------*/
/* -> DRAMCON0 : RAM Bank0 control register */
/*------------------------------------------------------------------*/
.EQU EDO_Mode0, 1 /* (EDO)0=Normal, 1=EDO DRAM */
.EQU CasPrechargeTime0, 0 /* (Tcp)0=1cycle,1=2cycle */
.EQU CasStrobeTime0, 1 /* (Tcs)0=1cycle ~ 3=4cycle */
.EQU DRAMCON0Reserved, 1 /* Must be set to 1 */
.EQU RAS2CASDelay0, 0 /* (Trc)0=1cycle,1=2cycle */
.EQU RASPrechargeTime0, 2 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU DRAMBasePtr0, (0x100<<10) /* =0x1000000 */
.EQU DRAMEndPtr0, (0x140<<20) /* =0x1200000 */
.EQU DRAMBasePtr0_S, (0x000<<10) /* =0x0000000 ;; REMAP */
.EQU DRAMEndPtr0_S, (0x040<<20) /* =0x0200000 */
.EQU NoColumnAddr0, 2 /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*------------------------------------------------------------------*/
.EQU Tcs0, (CasStrobeTime0<<1)
.EQU Tcp0, (CasPrechargeTime0<<3)
.EQU dumy0, (DRAMCON0Reserved<<4) /* dummy cycle */
.EQU Trc0, (RAS2CASDelay0<<7)
.EQU Trp0, (RASPrechargeTime0<<8)
.EQU CAN0, (NoColumnAddr0<<30)
.EQU rDRAMCON0, CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
.EQU rDRAMCON0_S, CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
/*------------------------------------------------------------------*/
.EQU SRAS2CASDelay0, 1 /* (Trc)0=1cycle,1=2cycle */
.EQU SRASPrechargeTime0, 3 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU SNoColumnAddr0, 0 /* 0=8bit,1=9bit,2=10bit,3=11bits */
.EQU SCAN0, (SNoColumnAddr0<<30)
.EQU STrc0, (SRAS2CASDelay0<<7)
.EQU STrp0, (SRASPrechargeTime0<<8)
.EQU rSDRAMCON0, SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0
.EQU rSDRAMCON0_S, SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0
/*------------------------------------------------------------------*/
/* -> DRAMCON1 : RAM Bank1 control register */
/*------------------------------------------------------------------*/
.EQU EDO_Mode1, 1 /* (EDO)0=Normal, 1=EDO DRAM */
.EQU CasPrechargeTime1, 0 /* (Tcp)0=1cycle,1=2cycle */
.EQU CasStrobeTime1, 1 /* (Tcs)0=1cycle ~ 3=4cycle */
.EQU DRAMCON1Reserved, 0 /* Must be set to 1 */
.EQU RAS2CASDelay1, 0 /* (Trc)0=1cycle,1=2cycle */
.EQU RASPrechargeTime1, 0 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU DRAMBasePtr1, (0x140<<10) /* =0x12000000 */
.EQU DRAMEndPtr1, (0x180<<20) /* =0x14000000 */
.EQU DRAMBasePtr1_S, 0x040<<10 /* =0x04000000 */
.EQU DRAMEndPtr1_S, 0x080<<20 /* =0x08000000 */
.EQU NoColumnAddr1, 2 /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*------------------------------------------------------------------*/
.EQU Tcs1, (CasStrobeTime1<<1)
.EQU Tcp1, (CasPrechargeTime1<<3)
.EQU dumy1, (DRAMCON1Reserved<<4) /* dummy cycle */
.EQU Trc1, (RAS2CASDelay1<<7)
.EQU Trp1, (RASPrechargeTime1<<8)
.EQU CAN1, (NoColumnAddr1<<30)
.EQU rDRAMCON1, CAN1+DRAMEndPtr1+DRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
.EQU rDRAMCON1_S, CAN1+DRAMEndPtr1_S+DRAMBasePtr1_S+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
/*------------------------------------------------------------------*/
.EQU SRAS2CASDelay1, 1 /* (Trc)0=1cycle,1=2cycle */
.EQU SRASPrechargeTime1, 1 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU SNoColumnAddr1, 0 /* 0=8bit,1=9bit,2=10bit,3=11bits */
.EQU SCAN1, (SNoColumnAddr1<<30)
.EQU STrc1, (SRAS2CASDelay1<<7)
.EQU STrp1, (SRASPrechargeTime1<<8)
.EQU rSDRAMCON1, SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+STrc1
.EQU rSDRAMCON1_S, SCAN1+DRAMEndPtr1_S+DRAMBasePtr1_S+STrp1+STrc1
/*------------------------------------------------------------------*/
/* -> DRAMCON2 : RAM Bank2 control register */
/*------------------------------------------------------------------*/
.EQU EDO_Mode2, 0 /* (EDO)0=Normal, 1=EDO DRAM */
.EQU CasPrechargeTime2, 0 /* (Tcp)0=1cycle,1=2cycle */
.EQU CasStrobeTime2, 1 /* (Tcs)0=1cycle ~ 3=4cycle */
.EQU DRAMCON2Reserved, 1 /* Must be set to 1 */
.EQU RAS2CASDelay2, 0 /* (Trc)0=1cycle,1=2cycle */
.EQU RASPrechargeTime2, 0 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU DRAMBasePtr2, (0x180<<10) /* =0x14000000 */
.EQU DRAMEndPtr2, (0x1C0<<20) /* =0x18000000 */
.EQU DRAMBasePtr2_S, (0x080<<10) /* =0x08000000 */
.EQU DRAMEndPtr2_S, (0x0C0<<20) /* =0x0C000000 */
.EQU NoColumnAddr2, 2 /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*------------------------------------------------------------------*/
.EQU Tcs2, (CasStrobeTime2<<1)
.EQU Tcp2, (CasPrechargeTime2<<3)
.EQU dumy2, (DRAMCON2Reserved<<4) /* dummy cycle */
.EQU Trc2, (RAS2CASDelay2<<7)
.EQU Trp2, (RASPrechargeTime2<<8)
.EQU CAN2, (NoColumnAddr2<<30)
.EQU rDRAMCON2, CAN2+DRAMEndPtr2+DRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
.EQU rDRAMCON2_S, CAN2+DRAMEndPtr2_S+DRAMBasePtr2_S+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
/*------------------------------------------------------------------*/
.EQU SRAS2CASDelay2, 1 /* (Trc)0=1cycle,1=2cycle */
.EQU SRASPrechargeTime2, 1 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU SNoColumnAddr2, 0 /* 0=8bit,1=9bit,2=10bit,3=11bits */
.EQU SCAN2, (SNoColumnAddr2<<30)
.EQU STrc2, (SRAS2CASDelay2<<7)
.EQU STrp2, (SRASPrechargeTime2<<8)
.EQU rSDRAMCON2, SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+STrc2
.EQU rSDRAMCON2_S, SCAN2+DRAMEndPtr2_S+DRAMBasePtr2_S+STrp2+STrc2
/*------------------------------------------------------------------*/
/* -> DRAMCON3 : RAM Bank3 control register */
/*------------------------------------------------------------------*/
.EQU EDO_Mode3, 0 /* (EDO)0=Normal, 1=EDO DRAM */
.EQU CasPrechargeTime3, 0 /* (Tcp)0=1cycle,1=2cycle */
.EQU CasStrobeTime3, 1 /* (Tcs)0=1cycle ~ 3=4cycle */
.EQU DRAMCON3Reserved, 1 /* Must be set to 1 */
.EQU RAS2CASDelay3, 0 /* (Trc)0=1cycle,1=2cycle */
.EQU RASPrechargeTime3, 0 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU DRAMBasePtr3, 0x1C0<<10 /* =0x14000000 */
.EQU DRAMEndPtr3, 0x200<<20 /* =0x18000000 */
.EQU DRAMBasePtr3_S, 0x0C0<<10 /* =0x0C000000 */
.EQU DRAMEndPtr3_S, 0x100<<20 /* =0x10000000 */
.EQU NoColumnAddr3, 2 /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*------------------------------------------------------------------*/
.EQU Tcs3, CasStrobeTime3<<1
.EQU Tcp3, CasPrechargeTime3<<3
.EQU dumy3, DRAMCON3Reserved<<4 /* dummy cycle */
.EQU Trc3, RAS2CASDelay3<<7
.EQU Trp3, RASPrechargeTime3<<8
.EQU CAN3, NoColumnAddr3<<30
.EQU rDRAMCON3, CAN3+DRAMEndPtr3+DRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
.EQU rDRAMCON3_S, CAN3+DRAMEndPtr3_S+DRAMBasePtr3_S+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
/*------------------------------------------------------------------*/
.EQU SRAS2CASDelay3, 1 /* (Trc)0=1cycle,1=2cycle */
.EQU SRASPrechargeTime3, 1 /* (Trp)0=1cycle ~ 3=4clcyle */
.EQU SNoColumnAddr3, 0 /* 0=8bit,1=9bit,2=10bit,3=11bits */
.EQU SCAN3, SNoColumnAddr3<<30
.EQU STrc3, SRAS2CASDelay3<<7
.EQU STrp3, SRASPrechargeTime3<<8
.EQU rSDRAMCON3, SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+STrc3
.EQU rSDRAMCON3_S, SCAN3+DRAMEndPtr3_S+DRAMBasePtr3_S+STrp3+STrc3
/*------------------------------------------------------------------*/
/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
/*------------------------------------------------------------------*/
.EQU RefCycle, 16 /* Unit [us], 1k refresh 16ms */
.EQU CASSetupTime, 0 /* 0=1cycle, 1=2cycle */
.EQU CASHoldTime, 0 /* 0=1cycle, 1=2cycle, 2=3cycle, */
/* 3=4cycle, 4=5cycle, */
.EQU RefCycleValue, ((2048+1-(RefCycle*fMCLK))<<21)
.EQU Tcsr, (CASSetupTime<<20) /* 1cycle */
.EQU Tcs, (CASHoldTime<<17)
.EQU ExtIOBase, 0x18360 /* Refresh enable, VSF=1 */
.EQU rREFEXTCON, RefCycleValue+Tcsr+Tcs+ExtIOBase
/*------------------------------------------------------------------*/
#.EQU SRefCycle, 16 /* Unit [us], 4k refresh 64ms */
.EQU SRefCycle, 8 /* Unit [us], 4k refresh 64ms */
.EQU ROWcycleTime, 3 /* 0=1cycle, 1=2cycle, 2=3cycle, */
/* 3=4cycle, 4=5cycle, */
.EQU SRefCycleValue, ((2048+1-(SRefCycle*fMCLK))<<21)
.EQU STrc, (ROWcycleTime<<17)
.EQU rSREFEXTCON, SRefCycleValue+STrc+ExtIOBase
/*------------------------------------------------------------------*/
/************************************/
/* KS32C50100 SPECIAL REGISTERS */
/************************************/
.EQU ASIC_BASE, 0x3ff0000
/* Interrupt Control */
.EQU INT_CNTRL_BASE, ASIC_BASE+0x4000 /* Define base of all interrupt */
/* controller registers */
.EQU IntMode, ASIC_BASE+0x4000
.EQU IntPend, ASIC_BASE+0x4004
.EQU IntMask, ASIC_BASE+0x4008
.EQU INTOFFSET, ASIC_BASE+0x4024
/* I/O Port Interface */
.EQU IOPMODE, ASIC_BASE+0x5000
.EQU IOPCON, ASIC_BASE+0x5004
.EQU IOPDATA, ASIC_BASE+0x5008
/* UART 0,1 */
.EQU UARTLCON0, ASIC_BASE+0xD000
.EQU UARTCONT0, ASIC_BASE+0xD004
.EQU UARTSTAT0, ASIC_BASE+0xD008
.EQU UARTTXH0, ASIC_BASE+0xD00C
.EQU UARTRXB0, ASIC_BASE+0xD010
.EQU UARTBRD0, ASIC_BASE+0xD014
.EQU UARTLCON1, ASIC_BASE+0xE000
.EQU UARTCONT1, ASIC_BASE+0xE004
.EQU UARTSTAT1, ASIC_BASE+0xE008
.EQU UARTTXH1, ASIC_BASE+0xE00C
.EQU UARTRXB1, ASIC_BASE+0xE010
.EQU UARTBRD1, ASIC_BASE+0xE014
/* TIMER 0,1 */
.EQU TIMER_BASE, ASIC_BASE+0x6000 /* Define base for all timer */
/* GDMA 0,1*/
.EQU GDMA0_RUN_ENABLE, 1 /* registers */
.EQU GDMA1_RUN_ENABLE, 1
#--------------------------------------------------------------------------------------
# END
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