macinit.c

~{WwU_J9SC5D~}ucos~{T4Bk#,1`RkA4=S5wJT>y?IRT#,4x~}uart~{2bJT~}

/*
 * Function : ResetPhyChip
 * Description : Reset The Phychip, Auto-Negotiation Enable 
 */
void ResetPhyChip(void)
{
	U32	value ;
	/* 其实这里光这样调用才是有问题的 */
//	if(MACCON&MACLoop) MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,DR_100MB|PHY_FULLDUPLEX) ;
//	else {

#if 1  /* This routine is not used, because have some error */
	// 1. Reset PHY chip
	MiiStationWrite(PHY_CNTL_REG, PHYHWADDR, RESET_PHY ) ;
	while ( !(MiiStationRead(PHY_CNTL_REG, PHYHWADDR) & RESET_PHY) )  ;

	// 2. Restart PHY auto-negotiation
	MiiStationWrite(PHY_CNTL_REG, PHYHWADDR, ENABLE_AN | RESTART_AN); 

	// 3. Wait until auto-negotiation complete
	while ( !(MiiStationRead(PHY_STATUS_REG, PHYHWADDR) & AN_COMPLETE) ) ;

	// 4. Read auto-negotiation status from PHY register
	value = MiiStationRead(PHY_ANLPAR_REG, PHYHWADDR)  ;

	// 5. Set PHY control register as auto-negotiation status 
	if ( (value & DR100_TX_FULL) ) {
		MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,DR_100MB|PHY_FULLDUPLEX) ;
		gDuplexValue = FullDup ;
	}
	else if ( (value & DR100_TX_HALF) )
		MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,DR_100MB) ;
	else if ( (value & DR10_TX_FULL) ) {
		MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,PHY_FULLDUPLEX) ;
		gDuplexValue = FullDup ;
	}
	else 	MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,0) ;
#endif
//	}

	//MiiStationWrite(PHY_CNTL_REG, PHYHWADDR, ENABLE_AN | RESTART_AN); 
	//MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,DR_100MB|PHY_FULLDUPLEX) ;
	//MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,DR_100MB) ;
	//MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,PHY_FULLDUPLEX) ;
	//MiiStationWrite(PHY_CNTL_REG,PHYHWADDR,0) ;
	//gDuplexValue = FullDup ;
}

/*
 * Function : MiiStationRead, MiiStationWrite  
 * Description : MII Interface Station Management Register Read or Write
 * Input : PhyInAddr(PHY internal register address)
 *         PhyAddr(PHY unique address)
 *         PhyWrData(When Write) 
 * Output: PhyRdData(WhenRead) 
 */
void MiiStationWrite(U32 PhyInAddr, U32 PhyAddr, U32 PhyWrData)
{
	STADATA = PhyWrData ;
	STACON = PhyInAddr | PhyAddr |  MiiBusy | PHYREGWRITE ;
	while( (STACON & MiiBusy) )  ;
	delay_physet() ;
}
U32 MiiStationRead(U32 PhyInAddr, U32 PhyAddr) 
{
	U32	PhyRdData ;
	STACON = PhyInAddr | PhyAddr |  MiiBusy ;
	while( (STACON & MiiBusy) )  ;
	PhyRdData = STADATA ;
	return PhyRdData ;
}

void delay_physet(void) 
{
	int i=1000 ;
	while(i--) ;
}


/*
 * Function : MAC_Tx_isr
 * Description : Interrupt Service Routine for MAC Tx
 */
void MAC_Tx_isr(void)
{   

	sFrameDescriptor *pTxFDptr;
	U32 *pFrameDataPtr ;
	U32 Status ;
	U32 CTxPtr ;

	CTxPtr = BDMATXPTR ;

	while ( gCTxFDPtr != CTxPtr )  { 
		pTxFDptr = (sFrameDescriptor *) gCTxFDPtr;

		// Check CPU ownership
		// if Owner is BDMA then break
		pFrameDataPtr = (U32 *)&pTxFDptr->FrameDataPtr;
		if ( (*pFrameDataPtr & fOwnership_BDMA) ) break ;
	
		Status = (pTxFDptr->StatusAndFrameLength >> 16) & 0xffff;
	
		if (Status & Comp) {
			gsMacTxStatus.MacTxGood++ ;
			//put_byte('T');
		}
		else
		{
			//put_byte('E');
			// Save Error status
			// Check each status, because, error can duplicated
			if (Status & Under) gsMacTxStatus.UnderErr++ ;
			if (Status & ExColl) gsMacTxStatus.ExCollErr++ ;
			if (Status & TxDeffer) gsMacTxStatus.TxDefferedErr++ ;
			if (Status & Paused) gsMacTxStatus.sPaused++ ;
			if (Status & Defer) gsMacTxStatus.DeferErr++ ;
			if (Status & NCarr) gsMacTxStatus.NCarrErr++ ;
			if (Status & SQErr) gsMacTxStatus.sSQE++ ;
			if (Status & LateColl) gsMacTxStatus.LateCollErr++ ;
			if (Status & TxPar) gsMacTxStatus.TxParErr++ ;
			if (Status & TxHalted) gsMacTxStatus.sTxHalted++ ;
    		
			// Set MAC/BDMA Tx control register for next use.
			MacDebugStatus() ; 
			ReadyMacTx() ;
		} // end if

		// Clear Framedata pointer already used.
		pTxFDptr->StatusAndFrameLength = (U32)0x0;

		gCTxFDPtr = (U32)pTxFDptr->NextFrameDescriptor ;
	} // end while loop

	MacTxDoneFlagForLoopBackCheck = 1 ;
}

/*
 * Function : MAC_Rx_isr
 * Description : Interrupt Service Routine for MAC Rx
 * Not Used
 */
void MAC_Rx_isr(void) 
{
	//Print("ISR MAC RX");
	put_byte('M');
}


/*
 * Function : BDMA_Tx_isr
 * Description : Interrupt Service Routine for BDMA Tx
 * Not Used
 */

void BDMA_Tx_isr(void) { }


/*
 * Function : BDMA_Rx_isr
 * Description : Interrupt Service Routine for BDMA Rx
 * Ethenet Frame is received in BDMA_Rx_isr
 */
/*
void BDMA_Rx_isr(void)
{
	sFrameDescriptor *pRxFDptr ;
	U32 RxStatus, FrameLength ;
	U32 CRxPtr;
	U32 sBdmaStat ;
	U8 *pFrameData ;
#if KS32C5000_BUG_FETCH
    	U32 FstData,FstDataSave,*FstFrameData ;
#endif

	// Step 1. Get current frame descriptor and status
	CRxPtr = BDMARXPTR ;
	gCRxFDPtr = CRxPtr;
	sBdmaStat = BDMASTAT ;

	// Step 2. Clear BDMA status register bit by write 1
	BDMASTAT |= S_BRxRDF ;
	gsBdmaRxStatus.BdmaRxCnt++ ;


	do {
		// Step 3. Check Null List Interrupt
		if ( BDMASTAT & S_BRxNL ) {
			BDMASTAT |= S_BRxNL ;
			gsBdmaRxStatus.BRxNLErr++ ;
			MacInitialize() ;
			break ;
		}

		// Step 4. Get Rx Frame Descriptor
		pRxFDptr = (sFrameDescriptor *)gCRxFDPtr ;
		RxStatus = (pRxFDptr->StatusAndFrameLength >> 16) & 0xffff;

		// Step 5. If Rx frame is good, then process received frame
		if((RxStatus & RxGood)&&!(RxStatus & OvMax)) {
			FrameLength = pRxFDptr->StatusAndFrameLength & 0xffff ; 
			pFrameData = (U8 *)pRxFDptr->FrameDataPtr ;
			gsBdmaRxStatus.BdmaRxGood++ ;
	     		//if ( !(gsBdmaRxStatus.BdmaRxGood%10000) ) 
				//Print("<R%d:%d>", tm0.tm_sec,gsBdmaRxStatus.BdmaRxGood) ;
				//Print("<FrameLength %d :%d>\r", FrameLength, gsBdmaRxStatus.BdmaRxGood) ;
*/			/*if((FrameLength==77)|(FrameLength==78)|(FrameLength==79)| \
				(FrameLength==141)|(FrameLength==142)|(FrameLength==143)| \
				(FrameLength==205)|(FrameLength==206)|(FrameLength==207)| \
				(FrameLength==269)|(FrameLength==270)|(FrameLength==271))*/
/*
				//Print("<FrameLength %d :%d RxStat %x>\r", FrameLength, gsBdmaRxStatus.BdmaRxGood, RxStatus) ;
#if KS32C5000_BUG_FETCH
                	FstFrameData = (U32 *)pRxFDptr->FrameDataPtr ;
			FstDataSave = *FstFrameData ;
			FstData = ( (FstDataSave<<24) & 0xFF000000 ) |\
				  ( (FstDataSave<<8)  & 0x00FF0000 ) |\
				  ( (FstDataSave>>24) & 0x000000FF ) |\
				  ( (FstDataSave>>8)  & 0x0000FF00 ) ;
	
			if (gPreviousStatusField == FstData) 
					pFrameData = pFrameData + 4 ;
#endif
	
			// Step 6. Get received frame to memory buffer
			GetRxFrameData(pFrameData, FrameLength, RxStatus) ;
			
		} else {
			//put_byte('q');
			// Step 7. If Rx frame has error, then process error frame
			gErrorPacketCnt++ ;

			// Save Error status
			// Check each status, because, error can duplicated
			if (RxStatus & OvMax) {
				gsMacRxStatus.OvMaxSize++ ;
				//put_byte('M');
				Print("\r\r OverSize error\r");
			}
			if (RxStatus & CtlRecd) gsMacRxStatus.sCtlRecd++ ;
			if (RxStatus & Rx10Stat) gsMacRxStatus.sRx10Stat++ ;
			if (RxStatus & AlignErr) gsMacRxStatus.AllgnErr++ ;
			if (RxStatus & CRCErr) gsMacRxStatus.sCRCErr++ ;
			if (RxStatus & Overflow) gsMacRxStatus.OverflowErr++ ;
			if (RxStatus & LongErr)	 gsMacRxStatus.sLongErr++ ;
			if (RxStatus & RxPar) gsMacRxStatus.RxParErr++ ;
			if (RxStatus & RxHalted) gsMacRxStatus.sRxHalted++ ;
		}

		// Step 8. Change ownership to BDMA for next use
		(pRxFDptr->FrameDataPtr) |= fOwnership_BDMA;

		// Save Current Status and Frame Length field, and clear
#if KS32C5000_BUG_FETCH
		gPreviousStatusField = pRxFDptr->StatusAndFrameLength ;
#endif
		//pRxFDptr->StatusAndFrameLength = (U32)0x0;

		// Step 9. Get Next Frame Descriptor pointer to process
		gCRxFDPtr = (U32)(pRxFDptr->NextFrameDescriptor) ;

	} while (CRxPtr != gCRxFDPtr);

	// Step 10. Check Notowner status
	if ( sBdmaStat & S_BRxNO ) {
		BDMASTAT |= S_BRxNO ;
		gsBdmaRxStatus.BRxNOErr++ ;

		ReadyMacRx() ;
	}

	BdmaRxDoneFlagForLoopBackCheck = 1 ; // only used for loopback test
}
*/



/*
 * Function : SendPacket
 * Description : Send ethernet frame function
 * Input : frame data pointer, frame length
 * Output : transmit ok(1) or error(0)
 */
/*
int SendPacket(U8 *Data,int Size)
{
	sFrameDescriptor	*psTxFD;
	U32			*pFrameDataPtr ;
	U8 			*pFrameData ;
	int			FrameLength ;


	// 1. Get Tx frame descriptor & data pointer
	psTxFD = (sFrameDescriptor *)gWTxFDPtr ;

	pFrameData = (U8 *)psTxFD->FrameDataPtr ;
	pFrameDataPtr = (U32 *)&psTxFD->FrameDataPtr;
	FrameLength = Size + sizeof(etheader) ;

	// 2. Check BDMA ownership
	if ( (*pFrameDataPtr & fOwnership_BDMA) ) return 0 ;

	// 3. Prepare Tx Frame data to Frame buffer
	memcpy ((U8 *)pFrameData,(U8 *)Data,FrameLength);

	// 4. Set TX Frame flag & Length Field
#ifdef LITTLE
	psTxFD->Reserved = (PaddingMode | CRCMode | SourceAddrIncrement | \
			LittleEndian | WidgetAlign00 | MACTxIntEn);
#else
	psTxFD->Reserved = (PaddingMode | CRCMode | SourceAddrIncrement | \
			BigEndian | WidgetAlign00 | MACTxIntEn);
#endif
	psTxFD->StatusAndFrameLength = (U32)(FrameLength & 0xffff);

	// 5. Cheange ownership to BDMA
	psTxFD->FrameDataPtr |= fOwnership_BDMA;

	// 6. Enable MAC and BDMA Tx control register
	MacTxGo();

	// 7. Change the Tx frame descriptor for next use
	gWTxFDPtr = (U32)(psTxFD->NextFrameDescriptor);

	return 1 ;
}
*/



/*
 * Function : ControlFrameTransfer
 * Description : Transfer Control Frame Data to another Host
 */
void ControlFrameTransfer(void) 
{
	char TransferPacket ;

	gBdmaTxCon  |= BTxCPIE ;
	ReadyMacTx() ;

	do 
	{
	Print("\r   $$ Select Transmit(T) or Quit(Q) ? ") ;
	TransferPacket = get_byte() ;
	if ( (TransferPacket == 'T') || (TransferPacket == 't') )
		{

		// Step 1. set destination address to CAM #0
		// Step 2. set source address to CAM #1
		// CAM #0 : 0000f0110000 (Destin Addr)
		// CAM #1 : 11f000000000 (Source Addr)
		VPint(CAM_BaseAddr) = 0x0000f011 ;	
		VPint(CAM_BaseAddr + 0x4) = 0x000011f0 ;	
		VPint(CAM_BaseAddr + 0x8) = 0x00000000 ;	

		// Step 3. set length or type field, opcode, and operand to CAM #18
		// CAM #18 : Opcode & Operand