netstart.cs

~{WwU_J9SC5D~}ucos~{T4Bk#,1`RkA4=S5wJT>y?IRT#,4x~}uart~{2bJT~}

reset
stop
; INTMSK
; Disabled all interrupt
memwrite 0x03ff4008 0xffffffff
; SYSCFG
; register = 0x03ff0000, Inner SRAM = 0x03fe0000
; enable cache, write can cache
; 0 SRAM, 8KB cache
memwrite 0x03ff0000 0xe7ffff96
; CLKCON
memwrite 0x03ff3000 0x00000000
; EXTACON0
memwrite 0x03ff3008 0x00000e92
; EXTACON1
memwrite 0x03ff300c 0x00000000
; EXTDBWTH
; 16 bits data bus width for FLASH
; 32 bits data bus width for SDRAM
memwrite 0x03ff3010 0x00103002
; ROMCON0
; Normal ROM
; tpa 5 cycles
; tacc reserved
; Base pointer 0x01800000
; Next pointer 0x01a00000 (2M)
memwrite 0x03ff3014 0x1a060070
; ROMCON1 - ROMCON5
; Disabled
;memwrite 0x03ff3018 0x00000000
;memwrite 0x03ff301c 0x00000000
;memwrite 0x03ff3020 0x00000000
;memwrite 0x03ff3024 0x00000000
;memwrite 0x03ff3028 0x00000000
; DRAMCON0
; Normal DRAM
; tCS 1 cycle
; tCP 2 cycles
; tRC 2 cycles
; tRP 2 cycles
; base pointer 0x00000000
; next pointer 0x00800000 (8M)
memwrite 0x03ff302c 0x08000100
; DRAMCON1-DRAMCON3
; Disabled
;memwrite 0x03ff3030 0x00000000
;memwrite 0x03ff3034 0x00000000
;memwrite 0x03ff3038 0x00000000
; REFEXTCON
; Base pointer 0x03600000
; Accessible to memory bank
; Enable DRAM refresh
; tCHR 5 cycles
; tCSR 1 cycle
; Refres count 0x4e1
;memwrite 0x03ff303c 0x9c2b8360
memwrite 0x03ff303c 0xce2b8360