time_sim.v

Verilog源码10.rar

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 19:15:44 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module d_latch (GATE, DATA, Q);
    input GATE;
    input DATA;
    output Q;

    wire n_12, n42, n38, \Q_reg/$1I7/LATCH/D_BUF , \Q_reg/$1I7/LATCH/G_INV , 
    \Q_reg/$1I7/LATCH/GE_BUF , \Q_reg/$1I7/LATCH/MUXAND0_OUT , 
    \Q_reg/$1I7/LATCH/MUXAND1_OUT , \Q_reg/$1I7/LATCH/MUXAND2_OUT , 
    \Q_reg/$1I7/LATCH/D_IN , \U20/$1I20_GTS_TRI , \U19/clkio_bufsig , 
    \U20/$1I20_GTS_TRI_2_INV , GND, VCC;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_INV U21 (.IN (n_12), .OUT (n38));
    X_IPAD GATE_PAD (.PAD (GATE));
    X_IPAD DATA_PAD (.PAD (DATA));
    X_OPAD Q_PAD (.PAD (Q));
    X_ONE VCC_23 (.OUT (VCC));
    X_BUF \Q_reg/$1I7/LATCH/D_BUF_7  (.IN (DATA), .OUT 
    (\Q_reg/$1I7/LATCH/D_BUF ));
    X_INV \Q_reg/$1I7/LATCH/G_INV_8  (.IN (n38), .OUT (\Q_reg/$1I7/LATCH/G_INV )
    );
    X_INV \Q_reg/$1I7/LATCH/GE_BUF_9  (.IN (VCC), .OUT 
    (\Q_reg/$1I7/LATCH/GE_BUF ));
    X_AND2 \Q_reg/$1I7/LATCH/MUXAND0  (.IN0 (n42), .IN1 
    (\Q_reg/$1I7/LATCH/GE_BUF ), .OUT (\Q_reg/$1I7/LATCH/MUXAND0_OUT ));
    X_AND2 \Q_reg/$1I7/LATCH/MUXAND1  (.IN0 (\Q_reg/$1I7/LATCH/D_BUF ), .IN1 
    (VCC), .OUT (\Q_reg/$1I7/LATCH/MUXAND1_OUT ));
    X_AND2 \Q_reg/$1I7/LATCH/MUXAND2  (.IN0 (\Q_reg/$1I7/LATCH/D_BUF ), .IN1 
    (n42), .OUT (\Q_reg/$1I7/LATCH/MUXAND2_OUT ));
    X_OR3 \Q_reg/$1I7/LATCH/MUXOR  (.IN0 (\Q_reg/$1I7/LATCH/MUXAND0_OUT ), .IN1 
    (\Q_reg/$1I7/LATCH/MUXAND1_OUT ), .IN2 (\Q_reg/$1I7/LATCH/MUXAND2_OUT ), 
    .OUT (\Q_reg/$1I7/LATCH/D_IN ));
    X_LATCH \Q_reg/$1I7/LATCH/INLATCH  (.IN (\Q_reg/$1I7/LATCH/D_IN ), .CLK 
    (\Q_reg/$1I7/LATCH/G_INV ), .SET (GND), .RST (GSR), .OUT (n42));
    X_BUF \U20/$1I20  (.IN (n42), .OUT (\U20/$1I20_GTS_TRI ));
    X_TRI \U20/$1I20_GTS_TRI_22  (.IN (\U20/$1I20_GTS_TRI ), .OUT (Q), .CTL 
    (\U20/$1I20_GTS_TRI_2_INV ));
    X_CKBUF \U19/clkbuf  (.IN (\U19/clkio_bufsig ), .OUT (n_12));
    X_BUF \U19/clkio_buf  (.IN (GATE), .OUT (\U19/clkio_bufsig ));
    X_INV \U20/$1I20_GTS_TRI_2_INV_24  (.IN (GTS), .OUT 
    (\U20/$1I20_GTS_TRI_2_INV ));
    X_ZERO GND_25 (.OUT (GND));
    X_PD NGD2VER_PD_18 (.OUT (GTS) );
    X_PD NGD2VER_PD_19 (.OUT (GSR) );
  endmodule