time_sim.v

Verilog源码15.rar

    (\add_35/u6/S0_1/CO_2 ), .OUT (\add_35/u6/S0_1/XOR2_F_SUM_1/2_0 ));
    X_XOR2 \add_35/u6/S0_1/XOR2_F_SUM_1/UPCNT37<2>  (.IN0 
    (\add_35/u6/S0_1/XOR2_F_SUM_1/2_0 ), .IN1 (n166), .OUT (UPCNT37[2]));
    X_FF \n168/DFF_OUT/FFX  (.IN (\n168/F ), .CLK (n108), .CE (VCC), .SET (GND)
    , .RST (GSR), .OUT (n168));
    X_FF \n168/DFF_OUT/FFY  (.IN (\n168/G ), .CLK (n108), .CE (VCC), .SET (GND)
    , .RST (GSR), .OUT (n167));
    X_BUF \n168/FGBLOCK/G2MUX  (.IN (\n168/FGBLOCK/COUT0 ), .OUT 
    (\n168/FGBLOCK/$1N8 ));
    X_BUF \n168/FGBLOCK/LUTRAM/CARRYBLK/A0BUF  (.IN (n168), .OUT 
    (\n168/FGBLOCK/COUT0 ));
    X_BUF \n168/FGBLOCK/LUTRAM/CARRYBLK/A1BUF_340  (.IN (n167), .OUT 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/A1BUF ));
    X_OR2 \n168/FGBLOCK/LUTRAM/CARRYBLK/OR1  (.IN0 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/AND4 ), .IN1 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/AND5 ), .OUT (\add_35/u6/S0_1/CO_2 ));
    X_AND2 \n168/FGBLOCK/LUTRAM/CARRYBLK/AND4_342  (.IN0 (\n168/FGBLOCK/COUT0 )
    , .IN1 (\n168/FGBLOCK/LUTRAM/CARRYBLK/XOR3 ), .OUT 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/AND4 ));
    X_INV \n168/FGBLOCK/LUTRAM/CARRYBLK/INV1_343  (.IN (\add_35/n19 ), .OUT 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/INV1 ));
    X_AND2 \n168/FGBLOCK/LUTRAM/CARRYBLK/AND5_344  (.IN0 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/AND5_0_INV ), .IN1 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/A1BUF ), .OUT 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/AND5 ));
    X_XOR2 \n168/FGBLOCK/LUTRAM/CARRYBLK/XOR3_345  (.IN0 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/INV1 ), .IN1 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/A1BUF ), .OUT 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/XOR3 ));
    X_INV \n168/FGBLOCK/LUTRAM/FLUT/OBUF  (.IN (n168), .OUT (\n168/F ));
    X_XOR2 \n168/FGBLOCK/LUTRAM/GLUT/XOR0  (.IN0 (\n168/FGBLOCK/$1N8 ), .IN1 
    (n167), .OUT (\n168/G ));
    X_AND3 \sub_36/u6/S0_1/CY4_1/CY4/AND3_A_214  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/C7 ), .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/AND3_A_1_INV )
    , .IN2 (\sub_36/u6/S0_1/CY4_1/CY4/AND3_A_2_INV ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_A ));
    X_AND3 \sub_36/u6/S0_1/CY4_1/CY4/AND3_B_215  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_B_0_INV ), .IN1 (\sub_36/u6/S0_1/CY4_1/C5 )
    , .IN2 (\sub_36/u6/S0_1/CY4_1/CY4/AND3_B_2_INV ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_B ));
    X_AND3 \sub_36/u6/S0_1/CY4_1/CY4/AND3_C_216  (.IN0 (n170), .IN1 
    (\sub_36/u6/S0_1/CY4_1/C5 ), .IN2 (\sub_36/u6/S0_1/CY4_1/C4 ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_C ));
    X_OR3 \sub_36/u6/S0_1/CY4_1/CY4/MUXC_OUT_217  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_A ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_B ), .IN2 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_C ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXC_OUT ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/C1_AND_218  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/C1 ), .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/C1_AND_1_INV )
    , .OUT (\sub_36/u6/S0_1/CY4_1/CY4/C1_AND ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/C0_AND_219  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/C0 ), .IN1 (\sub_36/n20 ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/C0_AND ));
    X_OR2 \sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT_220  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/C0_AND ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/C1_AND ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/F2_AND_221  (.IN0 (VCC), .IN1 
    (\sub_36/u6/S0_1/CY4_1/C7 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/F2_AND ));
    X_XOR2 \sub_36/u6/S0_1/CY4_1/CY4/F2_XOR_222  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/F2_AND ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/F2_XOR ));
    X_XOR2 \sub_36/u6/S0_1/CY4_1/CY4/F1_XOR_223  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/F2_XOR ), .IN1 (n170), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/F1_XOR ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/C2_AND_224  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/C2 ), .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/C2_AND_1_INV )
    , .OUT (\sub_36/u6/S0_1/CY4_1/CY4/C2_AND ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/C3_AND_225  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/C3 ), .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/F1_XOR ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/C3_AND ));
    X_OR2 \sub_36/u6/S0_1/CY4_1/CY4/MUXB_OUT_226  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/C2_AND ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/C3_AND ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXB_OUT ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/CIN_AND_227  (.IN0 (\sub_36/u6/S0_1/CO_2 )
    , .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/MUXB_OUT ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/CIN_AND ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/MUXC_AND_228  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXC_OUT ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXC_AND ));
    X_OR2 \sub_36/u6/S0_1/CY4_1/CY4/COUT0  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/CIN_AND ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXC_AND ), .OUT (\sub_36/u6/S0_1/CO_3 ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/G1_AND_230  (.IN0 (VCC), .IN1 
    (\sub_36/u6/S0_1/CY4_1/C7 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/G1_AND ));
    X_XOR2 \sub_36/u6/S0_1/CY4_1/CY4/G1_XOR_231  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/G1_AND ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/G1_XOR ));
    X_XOR2 \sub_36/u6/S0_1/CY4_1/CY4/G4_XOR_232  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/G1_XOR ), .IN1 (n169), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/G4_XOR ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/C6_AND_233  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/C6 ), .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/G4_XOR ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/C6_AND ));
    X_OR2 \sub_36/u6/S0_1/CY4_1/CY4/C6_OR_234  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/C6_OR_0_INV ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/C6_AND ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/C6_OR )
    );
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/COUT0_AND_235  (.IN0 
    (\sub_36/u6/S0_1/CO_3 ), .IN1 (\sub_36/u6/S0_1/CY4_1/CY4/C6_OR ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/COUT0_AND ));
    X_AND2 \sub_36/u6/S0_1/CY4_1/CY4/G4_AND_236  (.IN0 (n169), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/G4_AND_1_INV ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/G4_AND ));
    X_OR2 \sub_36/u6/S0_1/CY4_1/CY4/COUT  (.IN0 
    (\sub_36/u6/S0_1/CY4_1/CY4/COUT0_AND ), .IN1 
    (\sub_36/u6/S0_1/CY4_1/CY4/G4_AND ), .OUT (\sub_36/u6/S0_1/CO_4 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C0BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ONE ), .OUT (\sub_36/u6/S0_1/CY4_1/C0 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C1BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ZERO ), .OUT (\sub_36/u6/S0_1/CY4_1/C1 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C2BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ZERO ), .OUT (\sub_36/u6/S0_1/CY4_1/C2 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C3BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ONE ), .OUT (\sub_36/u6/S0_1/CY4_1/C3 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C4BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ONE ), .OUT (\sub_36/u6/S0_1/CY4_1/C4 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C5BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ONE ), .OUT (\sub_36/u6/S0_1/CY4_1/C5 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C6BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ONE ), .OUT (\sub_36/u6/S0_1/CY4_1/C6 ));
    X_BUF \sub_36/u6/S0_1/CY4_1/CY4_32/C7BUF  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ZERO ), .OUT (\sub_36/u6/S0_1/CY4_1/C7 ));
    X_ZERO \sub_36/u6/S0_1/CY4_1/CY4_32/X_ZERO  (.OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ZERO ));
    X_ONE \sub_36/u6/S0_1/CY4_1/CY4_32/X_ONE  (.OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4_32/ONE ));
    X_XOR2 \sub_36/u6/S0_1/XOR3_G_SUM_1/DNCNT44<3>/2_0  (.IN0 
    (\sub_36/u6/S0_1/XOR3_G_SUM_1/DNCNT44[3]/2_0_0_INV ), .IN1 
    (\sub_36/u6/S0_1/CO_3 ), .OUT (\sub_36/u6/S0_1/XOR3_G_SUM_1/2_0 ));
    X_XOR2 \sub_36/u6/S0_1/XOR3_G_SUM_1/DNCNT44<3>  (.IN0 
    (\sub_36/u6/S0_1/XOR3_G_SUM_1/2_0 ), .IN1 (n169), .OUT (DNCNT44[3]));
    X_XOR2 \sub_36/u6/S0_1/XOR2_F_SUM_1/DNCNT44<2>/2_0  (.IN0 
    (\sub_36/u6/S0_1/XOR2_F_SUM_1/DNCNT44[2]/2_0_0_INV ), .IN1 
    (\sub_36/u6/S0_1/CO_2 ), .OUT (\sub_36/u6/S0_1/XOR2_F_SUM_1/2_0 ));
    X_XOR2 \sub_36/u6/S0_1/XOR2_F_SUM_1/DNCNT44<2>  (.IN0 
    (\sub_36/u6/S0_1/XOR2_F_SUM_1/2_0 ), .IN1 (n170), .OUT (DNCNT44[2]));
    X_FF \n172/DFF_OUT/FFX  (.IN (\n172/F ), .CLK (n108), .CE (VCC), .SET (GSR)
    , .RST (GND), .OUT (n172));
    X_FF \n172/DFF_OUT/FFY  (.IN (\n172/G ), .CLK (n108), .CE (VCC), .SET (GSR)
    , .RST (GND), .OUT (n171));
    X_BUF \n172/FGBLOCK/G2MUX  (.IN (\n172/FGBLOCK/COUT0 ), .OUT 
    (\n172/FGBLOCK/$1N8 ));
    X_BUF \n172/FGBLOCK/LUTRAM/CARRYBLK/A0BUF  (.IN (n172), .OUT 
    (\n172/FGBLOCK/COUT0 ));
    X_BUF \n172/FGBLOCK/LUTRAM/CARRYBLK/A1BUF_358  (.IN (n171), .OUT 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/A1BUF ));
    X_OR2 \n172/FGBLOCK/LUTRAM/CARRYBLK/OR1  (.IN0 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/AND4 ), .IN1 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/AND5 ), .OUT (\sub_36/u6/S0_1/CO_2 ));
    X_AND2 \n172/FGBLOCK/LUTRAM/CARRYBLK/AND4_360  (.IN0 (\n172/FGBLOCK/COUT0 )
    , .IN1 (\n172/FGBLOCK/LUTRAM/CARRYBLK/XOR3 ), .OUT 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/AND4 ));
    X_INV \n172/FGBLOCK/LUTRAM/CARRYBLK/INV1_361  (.IN (\sub_36/n20 ), .OUT 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/INV1 ));
    X_AND2 \n172/FGBLOCK/LUTRAM/CARRYBLK/AND5_362  (.IN0 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/AND5_0_INV ), .IN1 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/A1BUF ), .OUT 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/AND5 ));
    X_XOR2 \n172/FGBLOCK/LUTRAM/CARRYBLK/XOR3_363  (.IN0 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/INV1 ), .IN1 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/A1BUF ), .OUT 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/XOR3 ));
    X_INV \n172/FGBLOCK/LUTRAM/FLUT/OBUF  (.IN (n172), .OUT (\n172/F ));
    X_XOR2 \n172/FGBLOCK/LUTRAM/GLUT/XOR0  (.IN0 
    (\n172/FGBLOCK/LUTRAM/GLUT/XOR0_0_INV ), .IN1 (n171), .OUT (\n172/G ));
    X_INV \add_35/u6/S0_1/CY4_1/CY4/AND3_A_1_INV_371  (.IN 
    (\add_35/u6/S0_1/CY4_1/C5 ), .OUT (\add_35/u6/S0_1/CY4_1/CY4/AND3_A_1_INV )
    );
    X_INV \add_35/u6/S0_1/CY4_1/CY4/AND3_A_2_INV_372  (.IN 
    (\add_35/u6/S0_1/CY4_1/C4 ), .OUT (\add_35/u6/S0_1/CY4_1/CY4/AND3_A_2_INV )
    );
    X_INV \add_35/u6/S0_1/CY4_1/CY4/AND3_B_0_INV_373  (.IN (\add_35/n19 ), .OUT 
    (\add_35/u6/S0_1/CY4_1/CY4/AND3_B_0_INV ));
    X_INV \add_35/u6/S0_1/CY4_1/CY4/AND3_B_2_INV_374  (.IN 
    (\add_35/u6/S0_1/CY4_1/C4 ), .OUT (\add_35/u6/S0_1/CY4_1/CY4/AND3_B_2_INV )
    );
    X_INV \add_35/u6/S0_1/CY4_1/CY4/C1_AND_1_INV_375  (.IN 
    (\add_35/u6/S0_1/CY4_1/C0 ), .OUT (\add_35/u6/S0_1/CY4_1/CY4/C1_AND_1_INV )
    );
    X_INV \add_35/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV_376  (.IN 
    (\add_35/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV ), .OUT 
    (\add_35/u6/S0_1/CY4_1/CY4/MUXA_OUT ));
    X_INV \add_35/u6/S0_1/CY4_1/CY4/C2_AND_1_INV_377  (.IN 
    (\add_35/u6/S0_1/CY4_1/C3 ), .OUT (\add_35/u6/S0_1/CY4_1/CY4/C2_AND_1_INV )
    );
    X_INV \add_35/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV_378  (.IN 
    (\add_35/u6/S0_1/CY4_1/CY4/MUXB_OUT ), .OUT 
    (\add_35/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV ));
    X_INV \add_35/u6/S0_1/CY4_1/CY4/C6_OR_0_INV_379  (.IN 
    (\add_35/u6/S0_1/CY4_1/C6 ), .OUT (\add_35/u6/S0_1/CY4_1/CY4/C6_OR_0_INV ));
    X_INV \add_35/u6/S0_1/CY4_1/CY4/G4_AND_1_INV_380  (.IN 
    (\add_35/u6/S0_1/CY4_1/CY4/C6_OR ), .OUT 
    (\add_35/u6/S0_1/CY4_1/CY4/G4_AND_1_INV ));
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/AND3_A_1_INV_381  (.IN 
    (\sub_36/u6/S0_1/CY4_1/C5 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/AND3_A_1_INV )
    );
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/AND3_A_2_INV_382  (.IN 
    (\sub_36/u6/S0_1/CY4_1/C4 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/AND3_A_2_INV )
    );
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/AND3_B_0_INV_383  (.IN (\sub_36/n20 ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/AND3_B_0_INV ));
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/AND3_B_2_INV_384  (.IN 
    (\sub_36/u6/S0_1/CY4_1/C4 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/AND3_B_2_INV )
    );
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/C1_AND_1_INV_385  (.IN 
    (\sub_36/u6/S0_1/CY4_1/C0 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/C1_AND_1_INV )
    );
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV_386  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXA_OUT ));
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/C2_AND_1_INV_387  (.IN 
    (\sub_36/u6/S0_1/CY4_1/C3 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/C2_AND_1_INV )
    );
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV_388  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXB_OUT ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV ));
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/C6_OR_0_INV_389  (.IN 
    (\sub_36/u6/S0_1/CY4_1/C6 ), .OUT (\sub_36/u6/S0_1/CY4_1/CY4/C6_OR_0_INV ));
    X_INV \sub_36/u6/S0_1/CY4_1/CY4/G4_AND_1_INV_390  (.IN 
    (\sub_36/u6/S0_1/CY4_1/CY4/C6_OR ), .OUT 
    (\sub_36/u6/S0_1/CY4_1/CY4/G4_AND_1_INV ));
    X_INV \add_35/u6/S0_1/XOR3_G_SUM_1/UPCNT37<3>/2_0_0_INV_391  (.IN 
    (\add_35/n19 ), .OUT (\add_35/u6/S0_1/XOR3_G_SUM_1/UPCNT37[3]/2_0_0_INV ));
    X_INV \add_35/u6/S0_1/XOR2_F_SUM_1/UPCNT37<2>/2_0_0_INV_392  (.IN 
    (\add_35/n19 ), .OUT (\add_35/u6/S0_1/XOR2_F_SUM_1/UPCNT37[2]/2_0_0_INV ));
    X_INV \sub_36/u6/S0_1/XOR3_G_SUM_1/DNCNT44<3>/2_0_0_INV_393  (.IN 
    (\sub_36/n20 ), .OUT (\sub_36/u6/S0_1/XOR3_G_SUM_1/DNCNT44[3]/2_0_0_INV ));
    X_INV \sub_36/u6/S0_1/XOR2_F_SUM_1/DNCNT44<2>/2_0_0_INV_394  (.IN 
    (\sub_36/n20 ), .OUT (\sub_36/u6/S0_1/XOR2_F_SUM_1/DNCNT44[2]/2_0_0_INV ));
    X_INV \U83/$1I20_GTS_TRI_2_INV_395  (.IN (GTS), .OUT 
    (\U83/$1I20_GTS_TRI_2_INV ));
    X_INV \U84/$1I20_GTS_TRI_2_INV_396  (.IN (GTS), .OUT 
    (\U84/$1I20_GTS_TRI_2_INV ));
    X_INV \U85/$1I20_GTS_TRI_2_INV_397  (.IN (GTS), .OUT 
    (\U85/$1I20_GTS_TRI_2_INV ));
    X_INV \U86/$1I20_GTS_TRI_2_INV_398  (.IN (GTS), .OUT 
    (\U86/$1I20_GTS_TRI_2_INV ));
    X_INV \U87/$1I20_GTS_TRI_2_INV_399  (.IN (GTS), .OUT 
    (\U87/$1I20_GTS_TRI_2_INV ));
    X_INV \U88/$1I20_GTS_TRI_2_INV_400  (.IN (GTS), .OUT 
    (\U88/$1I20_GTS_TRI_2_INV ));
    X_INV \U89/$1I20_GTS_TRI_2_INV_401  (.IN (GTS), .OUT 
    (\U89/$1I20_GTS_TRI_2_INV ));
    X_INV \U90/$1I20_GTS_TRI_2_INV_402  (.IN (GTS), .OUT 
    (\U90/$1I20_GTS_TRI_2_INV ));
    X_INV \n168/FGBLOCK/LUTRAM/CARRYBLK/AND5_0_INV_403  (.IN 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/XOR3 ), .OUT 
    (\n168/FGBLOCK/LUTRAM/CARRYBLK/AND5_0_INV ));
    X_INV \n172/FGBLOCK/LUTRAM/CARRYBLK/AND5_0_INV_404  (.IN 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/XOR3 ), .OUT 
    (\n172/FGBLOCK/LUTRAM/CARRYBLK/AND5_0_INV ));
    X_INV \n172/FGBLOCK/LUTRAM/GLUT/XOR0_0_INV_405  (.IN (\n172/FGBLOCK/$1N8 ), 
    .OUT (\n172/FGBLOCK/LUTRAM/GLUT/XOR0_0_INV ));
    X_ONE VCC_406 (.OUT (VCC));
    X_ZERO GND_407 (.OUT (GND));
  endmodule