time_sim.v

Verilog源码15.rar

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:57:43 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module no_gsr (CLOCK, RESET, UPCNT, DNCNT);
    input CLOCK;
    input RESET;
    output [3:0] UPCNT;
    output [3:0] DNCNT;

    wire n108, n109, n165, n166, n167, n168, n169, n170, n171, n172, 
    \add_24/n19 , \sub_25/n20 , \U83/$1I20_GTS_TRI , \U84/$1I20_GTS_TRI , 
    \U85/$1I20_GTS_TRI , \U86/$1I20_GTS_TRI , \U87/$1I20_GTS_TRI , 
    \U88/$1I20_GTS_TRI , \U89/$1I20_GTS_TRI , \U90/$1I20_GTS_TRI , 
    \UPCNT_reg[2]/$1I13_GSR_OR , \UPCNT_reg[3]/$1I13_GSR_OR , 
    \UPCNT_reg[0]/$1I13_GSR_OR , \UPCNT_reg[1]/$1I13_GSR_OR , 
    \DNCNT_reg[2]/$1I13_GSR_OR , \DNCNT_reg[3]/$1I13_GSR_OR , 
    \DNCNT_reg[0]/$1I13_GSR_OR , \DNCNT_reg[1]/$1I13_GSR_OR , 
    \add_24/u6/S0_1/CO_4 , \add_24/u6/S0_1/CO_3 , \add_24/u6/S0_1/CO_2 , 
    \add_24/u6/S0_1/CO_1 , \add_24/u6/S0_1/CY4_1/C0 , \add_24/u6/S0_1/CY4_1/C1 
    , \add_24/u6/S0_1/CY4_1/C2 , \add_24/u6/S0_1/CY4_1/C3 , 
    \add_24/u6/S0_1/CY4_1/C4 , \add_24/u6/S0_1/CY4_1/C5 , 
    \add_24/u6/S0_1/CY4_1/C6 , \add_24/u6/S0_1/CY4_1/C7 , 
    \add_24/u6/S0_1/CY4_1/CY4/AND3_A , \add_24/u6/S0_1/CY4_1/CY4/AND3_B , 
    \add_24/u6/S0_1/CY4_1/CY4/AND3_C , \add_24/u6/S0_1/CY4_1/CY4/MUXC_OUT , 
    \add_24/u6/S0_1/CY4_1/CY4/C1_AND , \add_24/u6/S0_1/CY4_1/CY4/C0_AND , 
    \add_24/u6/S0_1/CY4_1/CY4/MUXA_OUT , \add_24/u6/S0_1/CY4_1/CY4/F2_AND , 
    \add_24/u6/S0_1/CY4_1/CY4/F2_XOR , \add_24/u6/S0_1/CY4_1/CY4/F1_XOR , 
    \add_24/u6/S0_1/CY4_1/CY4/C2_AND , \add_24/u6/S0_1/CY4_1/CY4/C3_AND , 
    \add_24/u6/S0_1/CY4_1/CY4/MUXB_OUT , \add_24/u6/S0_1/CY4_1/CY4/CIN_AND , 
    \add_24/u6/S0_1/CY4_1/CY4/MUXC_AND , \add_24/u6/S0_1/CY4_1/CY4/G1_AND , 
    \add_24/u6/S0_1/CY4_1/CY4/G1_XOR , \add_24/u6/S0_1/CY4_1/CY4/G4_XOR , 
    \add_24/u6/S0_1/CY4_1/CY4/C6_AND , \add_24/u6/S0_1/CY4_1/CY4/C6_OR , 
    \add_24/u6/S0_1/CY4_1/CY4/COUT0_AND , \add_24/u6/S0_1/CY4_1/CY4/G4_AND , 
    \add_24/u6/S0_1/CY4_1/CY4_32/ONE , \add_24/u6/S0_1/CY4_1/CY4_32/ZERO , 
    \add_24/u6/S0_1/CY4_0/C0 , \add_24/u6/S0_1/CY4_0/C1 , 
    \add_24/u6/S0_1/CY4_0/C2 , \add_24/u6/S0_1/CY4_0/C3 , 
    \add_24/u6/S0_1/CY4_0/C4 , \add_24/u6/S0_1/CY4_0/C5 , 
    \add_24/u6/S0_1/CY4_0/C6 , \add_24/u6/S0_1/CY4_0/C7 , 
    \add_24/u6/S0_1/CY4_0/CY4/AND3_A , \add_24/u6/S0_1/CY4_0/CY4/AND3_B , 
    \add_24/u6/S0_1/CY4_0/CY4/AND3_C , \add_24/u6/S0_1/CY4_0/CY4/MUXC_OUT , 
    \add_24/u6/S0_1/CY4_0/CY4/C1_AND , \add_24/u6/S0_1/CY4_0/CY4/C0_AND , 
    \add_24/u6/S0_1/CY4_0/CY4/MUXA_OUT , \add_24/u6/S0_1/CY4_0/CY4/F2_AND , 
    \add_24/u6/S0_1/CY4_0/CY4/F2_XOR , \add_24/u6/S0_1/CY4_0/CY4/F1_XOR , 
    \add_24/u6/S0_1/CY4_0/CY4/C2_AND , \add_24/u6/S0_1/CY4_0/CY4/C3_AND , 
    \add_24/u6/S0_1/CY4_0/CY4/MUXB_OUT , \add_24/u6/S0_1/CY4_0/CY4/CIN_AND , 
    \add_24/u6/S0_1/CY4_0/CY4/MUXC_AND , \add_24/u6/S0_1/CY4_0/CY4/G1_AND , 
    \add_24/u6/S0_1/CY4_0/CY4/G1_XOR , \add_24/u6/S0_1/CY4_0/CY4/G4_XOR , 
    \add_24/u6/S0_1/CY4_0/CY4/C6_AND , \add_24/u6/S0_1/CY4_0/CY4/C6_OR , 
    \add_24/u6/S0_1/CY4_0/CY4/COUT0_AND , \add_24/u6/S0_1/CY4_0/CY4/G4_AND , 
    \add_24/u6/S0_1/CY4_0/CY4_33/ONE , \add_24/u6/S0_1/CY4_0/CY4_33/ZERO , 
    \add_24/u6/S0_1/XOR3_G_SUM_1/2_0 , \add_24/u6/S0_1/XOR2_F_SUM_1/2_0 , 
    \add_24/u6/S0_1/XOR1_G_SUM_0/2_0 , \sub_25/u6/S0_1/CO_4 , 
    \sub_25/u6/S0_1/CO_3 , \sub_25/u6/S0_1/CO_2 , \sub_25/u6/S0_1/CO_1 , 
    \sub_25/u6/S0_1/CY4_1/C0 , \sub_25/u6/S0_1/CY4_1/C1 , 
    \sub_25/u6/S0_1/CY4_1/C2 , \sub_25/u6/S0_1/CY4_1/C3 , 
    \sub_25/u6/S0_1/CY4_1/C4 , \sub_25/u6/S0_1/CY4_1/C5 , 
    \sub_25/u6/S0_1/CY4_1/C6 , \sub_25/u6/S0_1/CY4_1/C7 , 
    \sub_25/u6/S0_1/CY4_1/CY4/AND3_A , \sub_25/u6/S0_1/CY4_1/CY4/AND3_B , 
    \sub_25/u6/S0_1/CY4_1/CY4/AND3_C , \sub_25/u6/S0_1/CY4_1/CY4/MUXC_OUT , 
    \sub_25/u6/S0_1/CY4_1/CY4/C1_AND , \sub_25/u6/S0_1/CY4_1/CY4/C0_AND , 
    \sub_25/u6/S0_1/CY4_1/CY4/MUXA_OUT , \sub_25/u6/S0_1/CY4_1/CY4/F2_AND , 
    \sub_25/u6/S0_1/CY4_1/CY4/F2_XOR , \sub_25/u6/S0_1/CY4_1/CY4/F1_XOR , 
    \sub_25/u6/S0_1/CY4_1/CY4/C2_AND , \sub_25/u6/S0_1/CY4_1/CY4/C3_AND , 
    \sub_25/u6/S0_1/CY4_1/CY4/MUXB_OUT , \sub_25/u6/S0_1/CY4_1/CY4/CIN_AND , 
    \sub_25/u6/S0_1/CY4_1/CY4/MUXC_AND , \sub_25/u6/S0_1/CY4_1/CY4/G1_AND , 
    \sub_25/u6/S0_1/CY4_1/CY4/G1_XOR , \sub_25/u6/S0_1/CY4_1/CY4/G4_XOR , 
    \sub_25/u6/S0_1/CY4_1/CY4/C6_AND , \sub_25/u6/S0_1/CY4_1/CY4/C6_OR , 
    \sub_25/u6/S0_1/CY4_1/CY4/COUT0_AND , \sub_25/u6/S0_1/CY4_1/CY4/G4_AND , 
    \sub_25/u6/S0_1/CY4_1/CY4_32/ONE , \sub_25/u6/S0_1/CY4_1/CY4_32/ZERO , 
    \sub_25/u6/S0_1/CY4_0/C0 , \sub_25/u6/S0_1/CY4_0/C1 , 
    \sub_25/u6/S0_1/CY4_0/C2 , \sub_25/u6/S0_1/CY4_0/C3 , 
    \sub_25/u6/S0_1/CY4_0/C4 , \sub_25/u6/S0_1/CY4_0/C5 , 
    \sub_25/u6/S0_1/CY4_0/C6 , \sub_25/u6/S0_1/CY4_0/C7 , 
    \sub_25/u6/S0_1/CY4_0/CY4/AND3_A , \sub_25/u6/S0_1/CY4_0/CY4/AND3_B , 
    \sub_25/u6/S0_1/CY4_0/CY4/AND3_C , \sub_25/u6/S0_1/CY4_0/CY4/MUXC_OUT , 
    \sub_25/u6/S0_1/CY4_0/CY4/C1_AND , \sub_25/u6/S0_1/CY4_0/CY4/C0_AND , 
    \sub_25/u6/S0_1/CY4_0/CY4/MUXA_OUT , \sub_25/u6/S0_1/CY4_0/CY4/F2_AND , 
    \sub_25/u6/S0_1/CY4_0/CY4/F2_XOR , \sub_25/u6/S0_1/CY4_0/CY4/F1_XOR , 
    \sub_25/u6/S0_1/CY4_0/CY4/C2_AND , \sub_25/u6/S0_1/CY4_0/CY4/C3_AND , 
    \sub_25/u6/S0_1/CY4_0/CY4/MUXB_OUT , \sub_25/u6/S0_1/CY4_0/CY4/CIN_AND , 
    \sub_25/u6/S0_1/CY4_0/CY4/MUXC_AND , \sub_25/u6/S0_1/CY4_0/CY4/G1_AND , 
    \sub_25/u6/S0_1/CY4_0/CY4/G1_XOR , \sub_25/u6/S0_1/CY4_0/CY4/G4_XOR , 
    \sub_25/u6/S0_1/CY4_0/CY4/C6_AND , \sub_25/u6/S0_1/CY4_0/CY4/C6_OR , 
    \sub_25/u6/S0_1/CY4_0/CY4/COUT0_AND , \sub_25/u6/S0_1/CY4_0/CY4/G4_AND , 
    \sub_25/u6/S0_1/CY4_0/CY4_33/ONE , \sub_25/u6/S0_1/CY4_0/CY4_33/ZERO , 
    \sub_25/u6/S0_1/XOR3_G_SUM_1/2_0 , \sub_25/u6/S0_1/XOR2_F_SUM_1/2_0 , 
    \sub_25/u6/S0_1/XOR1_G_SUM_0/2_0 , \U81/clkio_bufsig , 
    \add_24/u6/S0_1/CY4_1/CY4/AND3_A_1_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/AND3_A_2_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/AND3_B_0_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/AND3_B_2_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/C1_AND_1_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/C2_AND_1_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/C6_OR_0_INV , 
    \add_24/u6/S0_1/CY4_1/CY4/G4_AND_1_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/AND3_A_1_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/AND3_A_2_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/AND3_B_0_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/AND3_B_2_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/C1_AND_1_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/MUXA_OUT_2_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/C2_AND_1_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/MUXC_AND_1_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/C6_OR_0_INV , 
    \add_24/u6/S0_1/CY4_0/CY4/G4_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/AND3_A_1_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/AND3_A_2_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/AND3_B_0_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/AND3_B_2_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/C1_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/C2_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/C6_OR_0_INV , 
    \sub_25/u6/S0_1/CY4_1/CY4/G4_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/AND3_A_1_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/AND3_A_2_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/AND3_B_0_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/AND3_B_2_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/C1_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/MUXA_OUT_2_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/C2_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/MUXC_AND_1_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/C6_OR_0_INV , 
    \sub_25/u6/S0_1/CY4_0/CY4/G4_AND_1_INV , 
    \add_24/u6/S0_1/XOR3_G_SUM_1/UPCNT37[3]/2_0_0_INV , 
    \add_24/u6/S0_1/XOR2_F_SUM_1/UPCNT37[2]/2_0_0_INV , 
    \add_24/u6/S0_1/XOR1_G_SUM_0/UPCNT37[1]/2_0_0_INV , 
    \sub_25/u6/S0_1/XOR3_G_SUM_1/DNCNT44[3]/2_0_0_INV , 
    \sub_25/u6/S0_1/XOR2_F_SUM_1/DNCNT44[2]/2_0_0_INV , 
    \sub_25/u6/S0_1/XOR1_G_SUM_0/DNCNT44[1]/2_0_0_INV , 
    \U83/$1I20_GTS_TRI_2_INV , \U84/$1I20_GTS_TRI_2_INV , 
    \U85/$1I20_GTS_TRI_2_INV , \U86/$1I20_GTS_TRI_2_INV , 
    \U87/$1I20_GTS_TRI_2_INV , \U88/$1I20_GTS_TRI_2_INV , 
    \U89/$1I20_GTS_TRI_2_INV , \U90/$1I20_GTS_TRI_2_INV , GND, VCC;
    wire [3:0] UPCNT37;
    wire [3:0] DNCNT44;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U82 (.IN (RESET), .OUT (n109));
    X_IPAD CLOCK_PAD (.PAD (CLOCK));
    X_IPAD RESET_PAD (.PAD (RESET));
    X_OPAD \UPCNT<3>_PAD  (.PAD (UPCNT[3]));
    X_OPAD \UPCNT<2>_PAD  (.PAD (UPCNT[2]));
    X_OPAD \UPCNT<1>_PAD  (.PAD (UPCNT[1]));
    X_OPAD \UPCNT<0>_PAD  (.PAD (UPCNT[0]));
    X_OPAD \DNCNT<3>_PAD  (.PAD (DNCNT[3]));
    X_OPAD \DNCNT<2>_PAD  (.PAD (DNCNT[2]));
    X_OPAD \DNCNT<1>_PAD  (.PAD (DNCNT[1]));
    X_OPAD \DNCNT<0>_PAD  (.PAD (DNCNT[0]));
    X_ONE \add_24/n19_ONE  (.OUT (\add_24/n19 ));
    X_ZERO \sub_25/n20_ZERO  (.OUT (\sub_25/n20 ));
    X_BUF \U83/$1I20  (.IN (n165), .OUT (\U83/$1I20_GTS_TRI ));
    X_TRI \U83/$1I20_GTS_TRI_327  (.IN (\U83/$1I20_GTS_TRI ), .OUT (UPCNT[3]), 
    .CTL (\U83/$1I20_GTS_TRI_2_INV ));
    X_BUF \U84/$1I20  (.IN (n166), .OUT (\U84/$1I20_GTS_TRI ));
    X_TRI \U84/$1I20_GTS_TRI_328  (.IN (\U84/$1I20_GTS_TRI ), .OUT (UPCNT[2]), 
    .CTL (\U84/$1I20_GTS_TRI_2_INV ));
    X_BUF \U85/$1I20  (.IN (n167), .OUT (\U85/$1I20_GTS_TRI ));
    X_TRI \U85/$1I20_GTS_TRI_329  (.IN (\U85/$1I20_GTS_TRI ), .OUT (UPCNT[1]), 
    .CTL (\U85/$1I20_GTS_TRI_2_INV ));
    X_BUF \U86/$1I20  (.IN (n168), .OUT (\U86/$1I20_GTS_TRI ));
    X_TRI \U86/$1I20_GTS_TRI_330  (.IN (\U86/$1I20_GTS_TRI ), .OUT (UPCNT[0]), 
    .CTL (\U86/$1I20_GTS_TRI_2_INV ));
    X_BUF \U87/$1I20  (.IN (n169), .OUT (\U87/$1I20_GTS_TRI ));
    X_TRI \U87/$1I20_GTS_TRI_331  (.IN (\U87/$1I20_GTS_TRI ), .OUT (DNCNT[3]), 
    .CTL (\U87/$1I20_GTS_TRI_2_INV ));
    X_BUF \U88/$1I20  (.IN (n170), .OUT (\U88/$1I20_GTS_TRI ));
    X_TRI \U88/$1I20_GTS_TRI_332  (.IN (\U88/$1I20_GTS_TRI ), .OUT (DNCNT[2]), 
    .CTL (\U88/$1I20_GTS_TRI_2_INV ));
    X_BUF \U89/$1I20  (.IN (n171), .OUT (\U89/$1I20_GTS_TRI ));
    X_TRI \U89/$1I20_GTS_TRI_333  (.IN (\U89/$1I20_GTS_TRI ), .OUT (DNCNT[1]), 
    .CTL (\U89/$1I20_GTS_TRI_2_INV ));
    X_BUF \U90/$1I20  (.IN (n172), .OUT (\U90/$1I20_GTS_TRI ));
    X_TRI \U90/$1I20_GTS_TRI_334  (.IN (\U90/$1I20_GTS_TRI ), .OUT (DNCNT[0]), 
    .CTL (\U90/$1I20_GTS_TRI_2_INV ));
    X_FF \UPCNT_reg<2>/$1I13  (.IN (UPCNT37[2]), .CLK (n108), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[2]/$1I13_GSR_OR ), .OUT (n166));
    X_OR2 \UPCNT_reg<2>/$1I13_GSR_OR_319  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\UPCNT_reg[2]/$1I13_GSR_OR ));
    X_FF \UPCNT_reg<3>/$1I13  (.IN (UPCNT37[3]), .CLK (n108), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[3]/$1I13_GSR_OR ), .OUT (n165));
    X_OR2 \UPCNT_reg<3>/$1I13_GSR_OR_320  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\UPCNT_reg[3]/$1I13_GSR_OR ));
    X_FF \UPCNT_reg<0>/$1I13  (.IN (UPCNT37[0]), .CLK (n108), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[0]/$1I13_GSR_OR ), .OUT (n168));
    X_OR2 \UPCNT_reg<0>/$1I13_GSR_OR_321  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\UPCNT_reg[0]/$1I13_GSR_OR ));
    X_FF \UPCNT_reg<1>/$1I13  (.IN (UPCNT37[1]), .CLK (n108), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[1]/$1I13_GSR_OR ), .OUT (n167));
    X_OR2 \UPCNT_reg<1>/$1I13_GSR_OR_322  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\UPCNT_reg[1]/$1I13_GSR_OR ));
    X_FF \DNCNT_reg<2>/$1I13  (.IN (DNCNT44[2]), .CLK (n108), .CE (VCC), .SET 
    (\DNCNT_reg[2]/$1I13_GSR_OR ), .RST (GND), .OUT (n170));
    X_OR2 \DNCNT_reg<2>/$1I13_GSR_OR_323  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\DNCNT_reg[2]/$1I13_GSR_OR ));
    X_FF \DNCNT_reg<3>/$1I13  (.IN (DNCNT44[3]), .CLK (n108), .CE (VCC), .SET 
    (\DNCNT_reg[3]/$1I13_GSR_OR ), .RST (GND), .OUT (n169));
    X_OR2 \DNCNT_reg<3>/$1I13_GSR_OR_324  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\DNCNT_reg[3]/$1I13_GSR_OR ));
    X_FF \DNCNT_reg<0>/$1I13  (.IN (DNCNT44[0]), .CLK (n108), .CE (VCC), .SET 
    (\DNCNT_reg[0]/$1I13_GSR_OR ), .RST (GND), .OUT (n172));
    X_OR2 \DNCNT_reg<0>/$1I13_GSR_OR_325  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\DNCNT_reg[0]/$1I13_GSR_OR ));
    X_FF \DNCNT_reg<1>/$1I13  (.IN (DNCNT44[1]), .CLK (n108), .CE (VCC), .SET 
    (\DNCNT_reg[1]/$1I13_GSR_OR ), .RST (GND), .OUT (n171));
    X_OR2 \DNCNT_reg<1>/$1I13_GSR_OR_326  (.IN0 (n109), .IN1 (GSR), .OUT 
    (\DNCNT_reg[1]/$1I13_GSR_OR ));
    X_INV \add_24/u6/S0_1/INV1_F_SUM_0  (.IN (n168), .OUT (UPCNT37[0]));
    X_AND3 \add_24/u6/S0_1/CY4_1/CY4/AND3_A_89  (.IN0 
    (\add_24/u6/S0_1/CY4_1/C7 ), .IN1 (\add_24/u6/S0_1/CY4_1/CY4/AND3_A_1_INV )
    , .IN2 (\add_24/u6/S0_1/CY4_1/CY4/AND3_A_2_INV ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_A ));
    X_AND3 \add_24/u6/S0_1/CY4_1/CY4/AND3_B_90  (.IN0 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_B_0_INV ), .IN1 (\add_24/u6/S0_1/CY4_1/C5 )
    , .IN2 (\add_24/u6/S0_1/CY4_1/CY4/AND3_B_2_INV ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_B ));
    X_AND3 \add_24/u6/S0_1/CY4_1/CY4/AND3_C_91  (.IN0 (n166), .IN1 
    (\add_24/u6/S0_1/CY4_1/C5 ), .IN2 (\add_24/u6/S0_1/CY4_1/C4 ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_C ));
    X_OR3 \add_24/u6/S0_1/CY4_1/CY4/MUXC_OUT_92  (.IN0 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_A ), .IN1 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_B ), .IN2 
    (\add_24/u6/S0_1/CY4_1/CY4/AND3_C ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/MUXC_OUT ));
    X_AND2 \add_24/u6/S0_1/CY4_1/CY4/C1_AND_93  (.IN0 
    (\add_24/u6/S0_1/CY4_1/C1 ), .IN1 (\add_24/u6/S0_1/CY4_1/CY4/C1_AND_1_INV )
    , .OUT (\add_24/u6/S0_1/CY4_1/CY4/C1_AND ));
    X_AND2 \add_24/u6/S0_1/CY4_1/CY4/C0_AND_94  (.IN0 
    (\add_24/u6/S0_1/CY4_1/C0 ), .IN1 (\add_24/n19 ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/C0_AND ));
    X_OR2 \add_24/u6/S0_1/CY4_1/CY4/MUXA_OUT_95  (.IN0 
    (\add_24/u6/S0_1/CY4_1/CY4/C0_AND ), .IN1 
    (\add_24/u6/S0_1/CY4_1/CY4/C1_AND ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV ));
    X_AND2 \add_24/u6/S0_1/CY4_1/CY4/F2_AND_96  (.IN0 (VCC), .IN1 
    (\add_24/u6/S0_1/CY4_1/C7 ), .OUT (\add_24/u6/S0_1/CY4_1/CY4/F2_AND ));
    X_XOR2 \add_24/u6/S0_1/CY4_1/CY4/F2_XOR_97  (.IN0 
    (\add_24/u6/S0_1/CY4_1/CY4/F2_AND ), .IN1 
    (\add_24/u6/S0_1/CY4_1/CY4/MUXA_OUT ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/F2_XOR ));
    X_XOR2 \add_24/u6/S0_1/CY4_1/CY4/F1_XOR_98  (.IN0 
    (\add_24/u6/S0_1/CY4_1/CY4/F2_XOR ), .IN1 (n166), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/F1_XOR ));
    X_AND2 \add_24/u6/S0_1/CY4_1/CY4/C2_AND_99  (.IN0 
    (\add_24/u6/S0_1/CY4_1/C2 ), .IN1 (\add_24/u6/S0_1/CY4_1/CY4/C2_AND_1_INV )
    , .OUT (\add_24/u6/S0_1/CY4_1/CY4/C2_AND ));
    X_AND2 \add_24/u6/S0_1/CY4_1/CY4/C3_AND_100  (.IN0 
    (\add_24/u6/S0_1/CY4_1/C3 ), .IN1 (\add_24/u6/S0_1/CY4_1/CY4/F1_XOR ), .OUT 
    (\add_24/u6/S0_1/CY4_1/CY4/C3_AND ));
    X_OR2 \add_24/u6/S0_1/CY4_1/CY4/MUXB_OUT_101  (.IN0 
    (\add_24/u6/S0_1/CY4_1/CY4/C2_AND ), .IN1 
    (\add_24/u6/S0_1/CY4_1/CY4/C3_AND ), .OUT