time_sim.v

Verilog源码13.rar

    \I_0/add_122/u6/S0_1/CY4_1/CY4/AND3_B_0_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/AND3_B_2_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/C1_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/C2_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/C6_OR_0_INV , 
    \I_0/add_122/u6/S0_1/CY4_1/CY4/G4_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/AND3_A_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/AND3_A_2_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/AND3_B_0_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/AND3_B_2_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/C1_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/MUXA_OUT_2_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/C2_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/MUXC_AND_1_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/C6_OR_0_INV , 
    \I_0/add_122/u6/S0_1/CY4_0/CY4/G4_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/AND3_A_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/AND3_A_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/AND3_B_0_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/AND3_B_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/C1_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/MUXA_OUT_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/C2_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/MUXC_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/C6_OR_0_INV , 
    \I_1/add_122/u6/S0_1/CY4_2/CY4/G4_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/AND3_A_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/AND3_A_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/AND3_B_0_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/AND3_B_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/C1_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/MUXA_OUT_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/C2_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/MUXC_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/C6_OR_0_INV , 
    \I_1/add_122/u6/S0_1/CY4_1/CY4/G4_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/AND3_A_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/AND3_A_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/AND3_B_0_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/AND3_B_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/C1_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/MUXA_OUT_2_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/C2_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/MUXC_AND_1_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/C6_OR_0_INV , 
    \I_1/add_122/u6/S0_1/CY4_0/CY4/G4_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/AND3_A_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/AND3_A_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/AND3_B_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/AND3_B_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/C1_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/MUXA_OUT_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/C2_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/MUXC_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/C6_OR_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_3/CY4/G4_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/AND3_A_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/AND3_A_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/AND3_B_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/AND3_B_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/C1_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/MUXA_OUT_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/C2_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/MUXC_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/C6_OR_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_2/CY4/G4_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/AND3_A_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/AND3_A_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/AND3_B_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/AND3_B_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/C1_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/MUXA_OUT_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/C2_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/MUXC_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/C6_OR_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_1/CY4/G4_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/AND3_A_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/AND3_A_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/AND3_B_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/AND3_B_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/C1_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/MUXA_OUT_2_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/C2_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/MUXC_AND_1_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/C6_OR_0_INV , 
    \I_0/add_136/u8/S0_1/CY4_0/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/AND3_A_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/AND3_A_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/AND3_B_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/C1_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/MUXA_OUT_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/C2_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/MUXC_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/C6_OR_0_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_5/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/AND3_A_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/AND3_A_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/AND3_B_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/C1_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/MUXA_OUT_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/C2_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/MUXC_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/C6_OR_0_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_4/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/AND3_A_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/AND3_A_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/AND3_B_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/C1_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/MUXA_OUT_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/C2_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/MUXC_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/C6_OR_0_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_3/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/AND3_A_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/AND3_A_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/AND3_B_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/C1_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/MUXA_OUT_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/C2_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/MUXC_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/C6_OR_0_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_2/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/AND3_A_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/AND3_A_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/AND3_B_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/C1_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/MUXA_OUT_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/C2_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/MUXC_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/C6_OR_0_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_1/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/AND3_A_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/AND3_A_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/AND3_B_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/C1_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/MUXA_OUT_2_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/C2_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/MUXC_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/C6_OR_0_INV , 
    \I_1/lt_130/u8/S0/SUB/CY4_0/CY4/G4_AND_1_INV , 
    \I_1/lt_130/u8/S0/SUB/AND3_CO_5_0_INV , 
    \I_1/lt_130/u8/S0/SUB/AND1_CO_5_1_INV , U170_2_INV, U172_2_INV, U176_2_INV, 
    U189_2_INV, U191_2_INV, U192_2_INV, U193_2_INV, U195_2_INV, U196_2_INV, 
    U197_2_INV, U201_2_INV, U205_2_INV, U207_2_INV, U208_2_INV, U219_2_INV, 
    U221_2_INV, U222_2_INV, U224_2_INV, U225_2_INV, U226_2_INV, U228_2_INV, 
    U229_2_INV, U230_2_INV, U237_2_INV, U245_2_INV, U246_2_INV, U248_2_INV, 
    U261_2_INV, U262_2_INV, U271_2_INV, U272_2_INV, U273_2_INV, U274_2_INV, 
    U282_2_INV, U283_2_INV, U285_2_INV, U289_2_INV, U292_2_INV, U295_2_INV, 
    U298_2_INV, U301_2_INV, U304_2_INV, U307_2_INV, U313_2_INV, U314_2_INV, 
    U318_2_INV, U324_2_INV, U325_2_INV, U329_2_INV, U330_2_INV, U331_2_INV, 
    U334_2_INV, U337_2_INV, U340_2_INV, U343_2_INV, U346_2_INV, U349_2_INV, 
    U355_2_INV, U401_2_INV, U405_2_INV, U407_2_INV, U411_2_INV, U412_2_INV, 
    U414_2_INV, U416_2_INV, U421_2_INV, U423_2_INV, U428_2_INV, U437_2_INV, 
    U438_2_INV, U441_2_INV, U443_2_INV, U450_2_INV, U452_2_INV, U456_2_INV, 
    U460_2_INV, U462_2_INV, U466_2_INV, U468_2_INV, U471_2_INV, U473_2_INV, 
    U477_2_INV, U481_2_INV, U482_2_INV, U483_2_INV, 
    \I_1/add_136/u8/S0_1/XOR6_F_SUM_3/I_1/ZCNT543[6]/2_0_0_INV , 
    \I_1/add_136/u8/S0_1/XOR5_G_SUM_2/I_1/ZCNT543[5]/2_0_0_INV , 
    \I_1/add_136/u8/S0_1/XOR4_F_SUM_2/I_1/ZCNT543[4]/2_0_0_INV , 
    \I_1/add_136/u8/S0_1/XOR3_G_SUM_1/I_1/ZCNT543[3]/2_0_0_INV , 
    \I_1/add_136/u8/S0_1/XOR2_F_SUM_1/I_1/ZCNT543[2]/2_0_0_INV , 
    \I_1/add_136/u8/S0_1/XOR1_G_SUM_0/I_1/ZCNT543[1]/2_0_0_INV , 
    \r337/u6/S0_1/XOR2_F_SUM_1/I_0/DCNT753[2]/2_0_0_INV , 
    \r337/u6/S0_1/XOR1_G_SUM_0/I_0/DCNT753[1]/2_0_0_INV , 
    \I_0/add_122/u6/S0_1/XOR4_F_SUM_2/I_0/ECNT511[4]/2_0_0_INV , 
    \I_0/add_122/u6/S0_1/XOR3_G_SUM_1/I_0/ECNT511[3]/2_0_0_INV , 
    \I_0/add_122/u6/S0_1/XOR2_F_SUM_1/I_0/ECNT511[2]/2_0_0_INV , 
    \I_0/add_122/u6/S0_1/XOR1_G_SUM_0/I_0/ECNT511[1]/2_0_0_INV , 
    \I_1/add_122/u6/S0_1/XOR4_F_SUM_2/I_1/ECNT511[4]/2_0_0_INV , 
    \I_1/add_122/u6/S0_1/XOR3_G_SUM_1/I_1/ECNT511[3]/2_0_0_INV , 
    \I_1/add_122/u6/S0_1/XOR2_F_SUM_1/I_1/ECNT511[2]/2_0_0_INV , 
    \I_1/add_122/u6/S0_1/XOR1_G_SUM_0/I_1/ECNT511[1]/2_0_0_INV , 
    \I_0/add_136/u8/S0_1/XOR6_F_SUM_3/I_0/ZCNT543[6]/2_0_0_INV , 
    \I_0/add_136/u8/S0_1/XOR5_G_SUM_2/I_0/ZCNT543[5]/2_0_0_INV , 
    \I_0/add_136/u8/S0_1/XOR4_F_SUM_2/I_0/ZCNT543[4]/2_0_0_INV , 
    \I_0/add_136/u8/S0_1/XOR3_G_SUM_1/I_0/ZCNT543[3]/2_0_0_INV , 
    \I_0/add_136/u8/S0_1/XOR2_F_SUM_1/I_0/ZCNT543[2]/2_0_0_INV , 
    \I_0/add_136/u8/S0_1/XOR1_G_SUM_0/I_0/ZCNT543[1]/2_0_0_INV , 
    \U178/n177_2_INV , \U181/n207_2_INV , \U185/n135_2_INV , \U188/n212_2_INV , 
    \U233/n142_2_INV , \U236/n247_2_INV , \U241/n173_2_INV , \U251/n171_2_INV , 
    \U254/n260_2_INV , \U257/I_1/ZCNT_E638_2_INV , \U264/n163_2_INV , 
    \U266/I_0/ZCNT_E638_2_INV , \U277/n152_2_INV , \U408/n144_2_INV , 
    \U417/n138_2_INV , \U426/n165_2_INV , \U433/n154_2_INV , 
    \U162/$1I20_GTS_TRI_2_INV , \U163/$1I20_GTS_TRI_2_INV , GND, VCC;
    wire [6:0] \I_1/ZCNT ;
    wire [6:0] \I_1/ZCNT543 ;
    wire [6:0] \I_0/ZCNT ;
    wire [2:0] \I_0/DCNT ;
    wire [2:0] \I_0/DCNT753 ;
    wire [4:0] \I_0/ECNT ;
    wire [4:0] \I_0/ECNT511 ;
    wire [4:0] \I_1/ECNT ;
    wire [4:0] \I_1/ECNT511 ;
    wire [6:0] \I_0/ZCNT543 ;
    wire [0:0] \I_0/n310 ;
    wire [4:0] \I_0/ECNT110 ;
    wire [2:0] \I_1/DCNT ;
    wire [2:2] \I_1/DCNT480 ;
    wire [0:0] \I_1/n310 ;
    wire [4:0] \I_1/ECNT110 ;
    wire [0:0] \I_1/n370 ;
    wire [0:0] \I_0/n370 ;
    wire [0:0] \I_0/n362 ;
    wire [0:0] \I_1/n362 ;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U155 (.IN (A_CHECK), .OUT (n59));
    X_BUF U156 (.IN (B_CHECK), .OUT (n60));
    X_BUF U157 (.IN (RESET), .OUT (n61));
    X_BUF U159 (.IN (CLKEN), .OUT (n63));
    X_BUF U160 (.IN (A_TICK), .OUT (n64));
    X_BUF U161 (.IN (B_TICK), .OUT (n65));
    X_INV U164 (.IN (n61), .OUT (\I_0/n796 ));
    X_INV U165 (.IN (n442), .OUT (\I_0/ST_INT489 ));
    X_INV U166 (.IN (n443), .OUT (\I_1/ST_INT489 ));
    X_INV U167 (.IN (n199), .OUT (n197));
    X_INV U168 (.IN (\I_1/ECNT_E477 ), .OUT (n198));
    X_OR2 U169 (.IN0 (\I_1/CLREVENT ), .IN1 (n197), .OUT (n200));
    X_AND2 U170 (.IN0 (n198), .IN1 (n65), .OUT (U170_2_INV));
    X_AND2 U171 (.IN0 (n200), .IN1 (n63), .OUT (\I_1/n319 ));
    X_AND2 U172 (.IN0 (n156), .IN1 (n152), .OUT (U172_2_INV));
    X_AND2 U173 (.IN0 (n201), .IN1 (\I_1/E2RQ ), .OUT (n202));
    X_OR2 U174 (.IN0 (n443), .IN1 (n202), .OUT (n158));
    X_FF \I_0/CLRZERO_reg  (.IN (\I_0/CLRZERO353 ), .CLK (n62), .CE (\I_0/n354 )
    , .SET (GND), .RST (\I_0/CLRZERO_reg_GSR_OR ), .OUT (\I_0/CLRZERO ));
    X_INV U175 (.IN (\I_0/ECNT_E477 ), .OUT (n203));
    X_AND2 U176 (.IN0 (\I_0/n301 ), .IN1 (n203), .OUT (U176_2_INV));
    X_OR2 U177 (.IN0 (\I_0/n301 ), .IN1 (\I_0/ECNT_E ), .OUT (n204));
    X_INV U179 (.IN (n207), .OUT (n208));
    X_INV U180 (.IN (\I_0/ZCNT_E638 ), .OUT (n206));
    X_OR2 U182 (.IN0 (\I_0/CLRZERO ), .IN1 (n208), .OUT (n137));
    X_FF \I_0/ST_INT_reg  (.IN (\I_0/ST_INT489 ), .CLK (n62), .CE (\I_0/n336 ), 
    .SET (GND), .RST (\I_0/ST_INT_reg_GSR_OR ), .OUT (n