var_cache.h

eCos1.31版

#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
//      var_cache.h
//
//      Variant HAL cache control API
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   nickg
// Contributors:nickg, jskov
// Date:        2000-04-02
// Purpose:     Variant cache control API
// Description: The macros defined here provide the HAL APIs for handling
//              cache control operations on the MPC8xx variant CPUs.
// Usage:       Is included via the architecture cache header:
//              #include <cyg/hal/hal_cache.h>
//              ...
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

#include <cyg/hal/ppc_regs.h>

#include <cyg/hal/plf_cache.h>


//-----------------------------------------------------------------------------
// Cache dimensions - these vary between the 8xx sub-models

#if defined(CYGPKG_HAL_POWERPC_MPC860)
// Data cache
#define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
#define HAL_DCACHE_WAYS                 2       // Associativity of the cache

// Instruction cache
#define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
#endif // defined(CYGPKG_HAL_POWERPC_MPC860)

#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
// Data cache
#define HAL_DCACHE_SIZE                 1024    // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
#define HAL_DCACHE_WAYS                 2       // Associativity of the cache

// Instruction cache
#define HAL_ICACHE_SIZE                 2048    // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)

#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))

//-----------------------------------------------------------------------------
// Global control of data cache

// Enable the data cache
#define HAL_DCACHE_ENABLE()                     \
    asm volatile ("sync;"                       \
                  "mtspr %0, %1;"               \
                  : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))

// Disable the data cache
#define HAL_DCACHE_DISABLE()                    \
    asm volatile ("sync;"                       \
                  "mtspr %0, %1;"               \
                  : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))

// Invalidate the entire cache
// Note: Any locked lines will not be invalidated.
#define HAL_DCACHE_INVALIDATE_ALL()                     \
    asm volatile ("sync;"                               \
                  "mtspr %0, %1;"                       \
                  : : "I" (CYGARC_REG_DC_CST),          \
                      "r" (CYGARC_REG_DC_CMD_IA))

// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()                                                     \
    CYG_MACRO_START                                                           \
    cyg_int32 i;                                                              \
    for (i = 0; i < HAL_DCACHE_SETS; i++){                                    \
        asm volatile ("sync;"                                                 \
                      "mtspr %0, %2;"                                         \
                      "mtspr %1, %4;"                                         \
                      "mtspr %0, %3;"                                         \
                      "mtspr %1, %4;"                                         \
                      : /* no output */                                       \
                      : /* %0 */ "I" (CYGARC_REG_DC_ADR),                     \
                        /* %1 */ "I" (CYGARC_REG_DC_CST),                     \
                        /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0                  \
                                      |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
                        /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1                  \
                                      |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
                        /* %4 */ "r" (CYGARC_REG_DC_CMD_FL));                 \
    }                                                                         \
    CYG_MACRO_END

// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_)                          \
    asm volatile ("mfspr  %0, %1;"                              \
                  "rlwinm %0,%0,1,31,31;"                       \
                  : "=r" (_state_) : "I" (CYGARC_REG_DC_CST))

// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)

// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )

//#define HAL_DCACHE_WRITETHRU_MODE       0
//#define HAL_DCACHE_WRITEBACK_MODE       1


// Load the contents of the given address range into the data cache 
// and then lock the cache so that it stays there.  

// Restrictions: This implementation only allows a single area to be
// locked at any one time. This area must be 2kB or less in size.

// Implementation: Flush entire cache, then invalidate it. This
// ensures that the fetched data go into way0.

#define HAL_DCACHE_LOCK(_base_, _size_)                                       \
    CYG_MACRO_START                                                           \
    cyg_int32 __scratch;                                                      \
    cyg_uint32 __base = (cyg_uint32)(_base_);                                 \
    cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS);      \
    cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE);                    \
    HAL_DCACHE_DISABLE();                                                     \
    HAL_DCACHE_SYNC ();                                                       \
    HAL_DCACHE_INVALIDATE_ALL ();                                             \
    HAL_DCACHE_ENABLE();                                                      \
    do {                                                                      \
        asm volatile ("lbz   %0,0(%1);"                                       \
                      "sync;"                                                 \
                      "mtspr %2, %4;"                                         \
                      "mtspr %3, %5;"                                         \
                      : /* %0 */ "=&r" (__scratch)                            \
                      : /* %1 */ "b" (__base),                                \
                        /* %2 */ "I" (CYGARC_REG_DC_ADR),                     \
                        /* %3 */ "I" (CYGARC_REG_DC_CST),                     \
                        /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0                  \
                                      |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
                        /* %5 */ "r" (CYGARC_REG_DC_CMD_LL));                 \
        __l++;                                                                \
        __base += HAL_DCACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

        
// Undo a previous lock operation

// Implementation: Unlocks entire cache.