var_intr.h

eCos1.31版

#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H

//==========================================================================
//
//      var_intr.h
//
//      AM31 Interrupt and clock support
//
//==========================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg, jskov,
//               gthomas, jlarmour
// Date:         1999-02-16
// Purpose:      AM31 Interrupt support
// Description:  The macros defined here provide the HAL APIs for handling
//               interrupts and the clock for AM31 variants of the MN10300
//               architecture.
//              
// Usage:
//              #include <cyg/hal/var_intr.h>
//              ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>

#include <cyg/hal/plf_intr.h>

//--------------------------------------------------------------------------

// The MN10300 has a somewhat complex interrupt structure. Besides the
// reset and NMI vectors there are seven maskable interrupt vectors
// which must point to code in the 64k starting at 0x40000000. There
// are also 25 Interrupt control groups, each of which can have 4
// interrupt lines attached, for a theoretical total of 100 interrupts
// (!). Some of these are dedicated to specific devices, other to
// external pins, and others are not connected to anything, resulting
// in only 45 that can actually be delivered. Each control group may
// be assigned one of seven interrupt levels, and is delivered to the
// corresponding vector. Software can then use a register to determine
// the delivering group and detect from there which interrupt has been
// delivered.
//
// The approach we will adopt at present is for the code attached to
// each vector to save state and jump via a table to a VSR. The
// default VSR will fully decode the delivered interrupt into a table
// of isr/data/object entries. VSR replacement will operate on the
// first level indirection table rather than the hardware
// vectors. This is the fastest mechanism, however it needs 100*3*4 +
// 7*4 = 1228 bytes for the tables.
// 

//--------------------------------------------------------------------------
// Interrupt vectors.

// The level-specific hardware vectors
// These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
#define CYGNUM_HAL_VECTOR_0                    0
#define CYGNUM_HAL_VECTOR_1                    1
#define CYGNUM_HAL_VECTOR_2                    2
#define CYGNUM_HAL_VECTOR_3                    3
#define CYGNUM_HAL_VECTOR_4                    4
#define CYGNUM_HAL_VECTOR_5                    5
#define CYGNUM_HAL_VECTOR_6                    6
#define CYGNUM_HAL_VECTOR_NMI_ENTRY            7
#define CYGNUM_HAL_VECTOR_TRAP                 8
#define CYGNUM_HAL_VECTOR_NMI                  9
#define CYGNUM_HAL_VECTOR_WATCHDOG             10
#define CYGNUM_HAL_VECTOR_SYSTEM_ERROR         11

#define CYGNUM_HAL_VSR_MIN                     0
#define CYGNUM_HAL_VSR_MAX                     11
#define CYGNUM_HAL_VSR_COUNT                   12

// Exception numbers. These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()

#define CYGNUM_HAL_EXCEPTION_NMI               CYGNUM_HAL_VECTOR_NMI
#define CYGNUM_HAL_EXCEPTION_WATCHDOG          CYGNUM_HAL_VECTOR_WATCHDOG
#define CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR      CYGNUM_HAL_VECTOR_SYSTEM_ERROR

#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS       CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR

#define CYGNUM_HAL_EXCEPTION_MIN               CYGNUM_HAL_VSR_MIN
#define CYGNUM_HAL_EXCEPTION_MAX               CYGNUM_HAL_VSR_MAX
#define CYGNUM_HAL_EXCEPTION_COUNT             CYGNUM_HAL_VSR_COUNT

// The decoded interrupts

#define CYGNUM_HAL_INTERRUPT_NMIRQ                0
#define CYGNUM_HAL_INTERRUPT_WATCHDOG             1
#define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR         2
#define CYGNUM_HAL_INTERRUPT_RESERVED_3           3

#define CYGNUM_HAL_INTERRUPT_RESERVED_4           4
#define CYGNUM_HAL_INTERRUPT_RESERVED_5           5
#define CYGNUM_HAL_INTERRUPT_RESERVED_6           6
#define CYGNUM_HAL_INTERRUPT_RESERVED_7           7

#define CYGNUM_HAL_INTERRUPT_TIMER_0              8
#define CYGNUM_HAL_INTERRUPT_RESERVED_9           9
#define CYGNUM_HAL_INTERRUPT_RESERVED_10          10
#define CYGNUM_HAL_INTERRUPT_RESERVED_11          11

#define CYGNUM_HAL_INTERRUPT_TIMER_1              12
#define CYGNUM_HAL_INTERRUPT_RESERVED_13          13
#define CYGNUM_HAL_INTERRUPT_RESERVED_14          14
#define CYGNUM_HAL_INTERRUPT_RESERVED_15          15

#define CYGNUM_HAL_INTERRUPT_TIMER_2              16
#define CYGNUM_HAL_INTERRUPT_RESERVED_17          17
#define CYGNUM_HAL_INTERRUPT_RESERVED_18          18
#define CYGNUM_HAL_INTERRUPT_RESERVED_19          19

#define CYGNUM_HAL_INTERRUPT_TIMER_3              20
#define CYGNUM_HAL_INTERRUPT_RESERVED_21          21
#define CYGNUM_HAL_INTERRUPT_RESERVED_22          22
#define CYGNUM_HAL_INTERRUPT_RESERVED_23          23

#define CYGNUM_HAL_INTERRUPT_TIMER_4              24
#define CYGNUM_HAL_INTERRUPT_RESERVED_25          25
#define CYGNUM_HAL_INTERRUPT_RESERVED_26          26
#define CYGNUM_HAL_INTERRUPT_RESERVED_27          27

#define CYGNUM_HAL_INTERRUPT_TIMER_5              28
#define CYGNUM_HAL_INTERRUPT_RESERVED_29          29
#define CYGNUM_HAL_INTERRUPT_RESERVED_30          30
#define CYGNUM_HAL_INTERRUPT_RESERVED_31          31

#define CYGNUM_HAL_INTERRUPT_TIMER_6              32
#define CYGNUM_HAL_INTERRUPT_RESERVED_33          33
#define CYGNUM_HAL_INTERRUPT_RESERVED_34          34
#define CYGNUM_HAL_INTERRUPT_RESERVED_35          35

#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A    36
#define CYGNUM_HAL_INTERRUPT_RESERVED_37          37
#define CYGNUM_HAL_INTERRUPT_RESERVED_38          38
#define CYGNUM_HAL_INTERRUPT_RESERVED_39          39

#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B    40
#define CYGNUM_HAL_INTERRUPT_RESERVED_41          41
#define CYGNUM_HAL_INTERRUPT_RESERVED_42          42
#define CYGNUM_HAL_INTERRUPT_RESERVED_43          43

#define CYGNUM_HAL_INTERRUPT_RESERVED_44          44
#define CYGNUM_HAL_INTERRUPT_RESERVED_45          45
#define CYGNUM_HAL_INTERRUPT_RESERVED_46          46
#define CYGNUM_HAL_INTERRUPT_RESERVED_47          47

#define CYGNUM_HAL_INTERRUPT_DMA0                 48
#define CYGNUM_HAL_INTERRUPT_RESERVED_49          49
#define CYGNUM_HAL_INTERRUPT_RESERVED_50          50
#define CYGNUM_HAL_INTERRUPT_RESERVED_51          51

#define CYGNUM_HAL_INTERRUPT_DMA1                 52
#define CYGNUM_HAL_INTERRUPT_RESERVED_53          53
#define CYGNUM_HAL_INTERRUPT_RESERVED_54          54
#define CYGNUM_HAL_INTERRUPT_RESERVED_55          55

#define CYGNUM_HAL_INTERRUPT_DMA2                 56
#define CYGNUM_HAL_INTERRUPT_RESERVED_57          57
#define CYGNUM_HAL_INTERRUPT_RESERVED_58          58
#define CYGNUM_HAL_INTERRUPT_RESERVED_59          59

#define CYGNUM_HAL_INTERRUPT_DMA3                 60
#define CYGNUM_HAL_INTERRUPT_RESERVED_61          61
#define CYGNUM_HAL_INTERRUPT_RESERVED_62          62
#define CYGNUM_HAL_INTERRUPT_RESERVED_63          63

#define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX          64