📄 var_arch.h
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#ifndef CYGONCE_HAL_VAR_ARCH_H#define CYGONCE_HAL_VAR_ARCH_H//==========================================================================//// var_arch.h//// Architecture specific abstractions////==========================================================================//####COPYRIGHTBEGIN####// // ------------------------------------------- // The contents of this file are subject to the Red Hat eCos Public License // Version 1.1 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://www.redhat.com/ // // Software distributed under the License is distributed on an "AS IS" // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the // License for the specific language governing rights and limitations under // the License. // // The Original Code is eCos - Embedded Configurable Operating System, // released September 30, 1998. // // The Initial Developer of the Original Code is Red Hat. // Portions created by Red Hat are // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. // All Rights Reserved. // ------------------------------------------- // //####COPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s): nickg// Contributors: nickg// Date: 1999-02-17// Purpose: Define architecture abstractions// Description: This file contains any extra or modified definitions for// this variant of the architecture.// Usage: #include <cyg/hal/var_arch.h>// //####DESCRIPTIONEND####////==========================================================================#include <pkgconf/hal.h>#include <cyg/infra/cyg_type.h>//--------------------------------------------------------------------------// Processor saved states:typedef struct HAL_SavedRegisters{ // These are common to all saved states and are in the order // stored and loaded by the movm instruction. CYG_ADDRWORD vector; /* Vector number/dummy */ CYG_ADDRWORD lar; /* Loop address register */ CYG_ADDRWORD lir; /* Loop instruction register */ CYG_ADDRWORD mdr; /* Multiply/Divide register */ CYG_ADDRWORD a1; CYG_ADDRWORD a0; CYG_ADDRWORD d1; CYG_ADDRWORD d0; CYG_ADDRWORD a3; CYG_ADDRWORD a2; CYG_ADDRWORD d3; CYG_ADDRWORD d2; /* On interrupts the PC and PSW are pushed automatically by the */ /* CPU and SP is pushed for debugging reasons. On a thread switch */ /* the saved context is made to look the same. */ CYG_ADDRWORD sp; /* Saved copy of SP in some states */ CYG_ADDRWORD psw; /* Status word */ CYG_ADDRWORD pc; /* Program Counter */ } HAL_SavedRegisters;//--------------------------------------------------------------------------#endif // CYGONCE_HAL_VAR_ARCH_H// End of var_arch.h
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