plf_intr.h

eCos1.31版

#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H

//==========================================================================
//
//      plf_intr.h
//
//      VRC4373 Interrupt and clock support
//
//==========================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg, jskov,
//               gthomas, jlarmour
// Date:         1999-02-16
// Purpose:      Define Interrupt support
// Description:  The macros defined here provide the HAL APIs for handling
//               interrupts and the clock for the VRC4373 board.
//              
// Usage:
//              #include <cyg/hal/plf_intr.h>
//              ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>

//--------------------------------------------------------------------------
// Interrupt controller stuff.

// The first 6 correspond to the interrupt lines in the status/cause regs
#define CYGNUM_HAL_INTERRUPT_VRC4373            0
#define CYGNUM_HAL_INTERRUPT_IPL0               1
#define CYGNUM_HAL_INTERRUPT_IPL1               2
#define CYGNUM_HAL_INTERRUPT_IPL2               3
#define CYGNUM_HAL_INTERRUPT_POWER              4
#define CYGNUM_HAL_INTERRUPT_COMPARE            5
// The next 32 correspond to the interrupt lines in the 4372 interrupt
// controller. These are decoded from the controller when an interrupt
// on any of the IPL[0:2] lines in signalled.
#define CYGNUM_HAL_INTERRUPT_REALTIME_A         6
#define CYGNUM_HAL_INTERRUPT_REALTIME_B         7
#define CYGNUM_HAL_INTERRUPT_DUART              8
#define CYGNUM_HAL_INTERRUPT_TIMER              9
#define CYGNUM_HAL_INTERRUPT_PARALLEL           10
#define CYGNUM_HAL_INTERRUPT_PCI_INTA           11
#define CYGNUM_HAL_INTERRUPT_PCI_INTB           12
#define CYGNUM_HAL_INTERRUPT_PCI_INTC           13
#define CYGNUM_HAL_INTERRUPT_PCI_INTD           14
#define CYGNUM_HAL_INTERRUPT_INT_9              15
#define CYGNUM_HAL_INTERRUPT_INT_10             16
#define CYGNUM_HAL_INTERRUPT_INT_11             17
#define CYGNUM_HAL_INTERRUPT_INT_12             18
#define CYGNUM_HAL_INTERRUPT_INT_13             19
#define CYGNUM_HAL_INTERRUPT_DMA_0              20
#define CYGNUM_HAL_INTERRUPT_DMA_1              21
#define CYGNUM_HAL_INTERRUPT_DMA_2              22
#define CYGNUM_HAL_INTERRUPT_DMA_3              23
#define CYGNUM_HAL_INTERRUPT_TICK_0             24
#define CYGNUM_HAL_INTERRUPT_TICK_1             25
#define CYGNUM_HAL_INTERRUPT_UNUSED_20          26
#define CYGNUM_HAL_INTERRUPT_UNUSED_21          27
#define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT         28
#define CYGNUM_HAL_INTERRUPT_PCI_PERR           29
#define CYGNUM_HAL_INTERRUPT_PCI_SERR           30
#define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA         31
#define CYGNUM_HAL_INTERRUPT_PCI_REC_TA         32
#define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA         33
#define CYGNUM_HAL_INTERRUPT_PCI_ADD            34
#define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR        35
#define CYGNUM_HAL_INTERRUPT_UNUSED_30          36
#define CYGNUM_HAL_INTERRUPT_UNUSED_31          37

// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN                     0
#define CYGNUM_HAL_ISR_MAX                     37
#define CYGNUM_HAL_ISR_COUNT                   38

// The vector used by the Real time clock. The default here is to use
// interrupt 5, which is connected to the counter/comparator registers
// in many MIPS variants.

#ifndef CYGNUM_HAL_INTERRUPT_RTC
#define CYGNUM_HAL_INTERRUPT_RTC            CYGNUM_HAL_INTERRUPT_COMPARE
#endif

#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED

//--------------------------------------------------------------------------
// controller access code

#define CYGHWR_HAL_MIPS_VRC4373_BASE            0xbc000000
#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL        (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG       (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS       (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0      (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0      (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1      (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1      (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2      (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2      (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220)

#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF   8

// Array which stores the configured priority levels for the configured
// interrupts.
externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];

#define HAL_INTERRUPT_MASK( _vector_ )                                          \
CYG_MACRO_START                                                                 \
    if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE )                              \
    {                                                                           \
        asm volatile (                                                          \