hal_arch.h

eCos1.31版

#ifndef CYGONCE_HAL_HAL_ARCH_H
#define CYGONCE_HAL_HAL_ARCH_H

//==========================================================================
//
//      hal_arch.h
//
//      Architecture specific abstractions
//
//==========================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg
// Date:         1999-02-17
// Purpose:      Define architecture abstractions
// Usage:        #include <cyg/hal/hal_arch.h>
//              
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

#include <cyg/hal/var_arch.h>

//--------------------------------------------------------------------------
// Processor saved states:
// The layout of this structure is also defined in "arch.inc", for assembly
// code. Do not change this without changing that (or vice versa).

#ifdef CYGHWR_HAL_MIPS_64BIT
# define CYG_HAL_MIPS_REG CYG_WORD64
# define CYG_HAL_MIPS_REG_SIZE 8
#else
# define CYG_HAL_MIPS_REG CYG_WORD32
# define CYG_HAL_MIPS_REG_SIZE 4
#endif

#if defined(CYGHWR_HAL_MIPS_FPU)
# if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
#  define CYG_HAL_FPU_REG CYG_WORD64
# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
#  define CYG_HAL_FPU_REG CYG_WORD32
# else
# error MIPS FPU register size not defined
# endif
#endif

typedef struct 
{
    // These are common to all saved states
    CYG_HAL_MIPS_REG    d[32];          /* Data regs                    */
    CYG_HAL_MIPS_REG    hi;             /* hi word of mpy/div reg       */
    CYG_HAL_MIPS_REG    lo;             /* lo word of mpy/div reg       */
#ifdef CYGHWR_HAL_MIPS_FPU
    CYG_HAL_FPU_REG     f[32];          /* FPU registers                */
    CYG_ADDRWORD        fcr31;          /* FPU control/status register  */
    CYG_ADDRWORD        fppad;          /* Dummy location to make this  */
                                        /* structure a multiple of 8    */
                                        /* bytes long.                  */
#endif
    
    // These are only saved for exceptions and interrupts
    CYG_ADDRWORD        vector;         /* Vector number                */
    CYG_ADDRWORD        pc;             /* Program Counter              */
    CYG_ADDRWORD        sr;             /* Status Reg                   */
    CYG_ADDRWORD        cache;          /* Cache control register       */


    // These are only saved for exceptions, and are not restored
    // when continued.
    CYG_ADDRWORD        cause;          /* Exception cause register     */
    CYG_ADDRWORD        badvr;          /* Bad virtual address reg      */
    CYG_ADDRWORD        prid;           /* Processor Version            */
    CYG_ADDRWORD        config;         /* Config register              */
} HAL_SavedRegisters;

//--------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.

externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );

//--------------------------------------------------------------------------
// Bit manipulation macros

externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);

#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);

#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);

//--------------------------------------------------------------------------
// Context Initialization


// Optional FPU context initialization
#ifdef CYGHWR_HAL_MIPS_FPU
#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )                             \
{                                                                               \
    for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|0xFF00|_i_;       \
    (_regs_)->fcr31 = 0x01000000;                                               \
}
#else
#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )
#endif


// Initialize the context of a thread.
// Arguments:
// _sparg_ name of variable containing current sp, will be written with new sp
// _thread_ thread object address, passed as argument to entry point
// _entry_ entry point address.
// _id_ bit pattern used in initializing registers, for debugging.
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )                     \
{                                                                                       \
    register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56;                                    \
    register HAL_SavedRegisters *_regs_;                                                \
    int _i_;                                                                            \
    _sp_ = _sp_ & 0xFFFFFFF0;                                                           \
    _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0);  \
    for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_;                      \
    HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ );                                        \
    (_regs_)->d[29] = (CYG_HAL_MIPS_REG)(_sp_);       /* SP = top of stack      */      \
    (_regs_)->d[04] = (CYG_HAL_MIPS_REG)(_thread_);   /* R4 = arg1 = thread ptr */      \
    (_regs_)->lo = 0;                                 /* LO = 0                 */      \
    (_regs_)->hi = 0;                                 /* HI = 0                 */      \
    (_regs_)->d[30] = (CYG_HAL_MIPS_REG)(_sp_);       /* FP = top of stack      */      \
    (_regs_)->d[31] = (CYG_HAL_MIPS_REG)(_entry_);    /* RA(d[31]) = entry point*/      \
    (_regs_)->pc = (CYG_WORD)(_entry_);               /* PC = entry point       */      \
    (_regs_)->sr  = 0x00000001;                       /* SR = ls 3 bits only    */      \
    _sparg_ = (CYG_ADDRESS)_regs_;                                                      \
}

//--------------------------------------------------------------------------
// Context switch macros.
// The arguments are pointers to locations where the stack pointer
// of the current thread is to be stored, and from where the sp of the
// next thread is to be fetched.

externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
externC void hal_thread_load_context( CYG_ADDRESS to )
    __attribute__ ((noreturn));

#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
        hal_thread_switch_context( (CYG_ADDRESS)_tspptr_,               \
                                   (CYG_ADDRESS)_fspptr_);

#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );

//--------------------------------------------------------------------------
// Execution reorder barrier.
// When optimizing the compiler can reorder code. In multithreaded systems
// where the order of actions is vital, this can sometimes cause problems.
// This macro may be inserted into places where reordering should not happen.
// The "memory" keyword is potentially unnecessary, but it is harmless to