hal_intr.h

eCos1.31版

#define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
// use them to declare these extern however you want:
//       extern char HAL_INTERRUPT_STACK_BASE[];
//       extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif

//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros

#define HAL_INTERRUPT_IN_USE( _vector_, _state_)                          \
    CYG_MACRO_START                                                       \
    cyg_uint32 _index_;                                                   \
    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                           \
                                                                          \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
        (_state_) = 0;                                                    \
    else                                                                  \
        (_state_) = 1;                                                    \
    CYG_MACRO_END

#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )         \
    CYG_MACRO_START                                                       \
    cyg_uint32 _index_;                                                   \
    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                           \
                                                                          \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
    {                                                                     \
        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_;             \
        hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_;              \
        hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_;           \
    }                                                                     \
    CYG_MACRO_END

#define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                         \
    CYG_MACRO_START                                                     \
    cyg_uint32 _index_;                                                 \
    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                         \
                                                                        \
    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ )         \
    {                                                                   \
        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
        hal_interrupt_data[_index_] = 0;                                \
        hal_interrupt_objects[_index_] = 0;                             \
    }                                                                   \
    CYG_MACRO_END

#define HAL_VSR_GET( _vector_, _pvsr_ )                                 \
    *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
    

#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ )               \
    CYG_MACRO_START                                             \
    if( _poldvsr_ != NULL )                                     \
        *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_];    \
    hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;               \
    CYG_MACRO_END

// This is an ugly name, but what it means is: grab the VSR back to eCos
// internal handling, or if you like, the default handler.  But if
// cooperating with GDB and CygMon, the default behaviour is to pass most
// exceptions to CygMon.  This macro undoes that so that eCos handles the
// exception.  So use it with care.

externC void cyg_hal_default_interrupt_vsr( void );
externC void cyg_hal_default_exception_vsr( void );
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ )                    \
    CYG_MACRO_START                                                           \
    if( (void*)_poldvsr_ != (void*)NULL )                                     \
        *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_];                  \
    hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ )           \
                              ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr    \
                              : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
    CYG_MACRO_END


//--------------------------------------------------------------------------
// Interrupt controller access
//
// Note: These macros work only on a unit basis ; if one source in a
// unit (such as SCI) is unmasked, all sources of that unit get
// unmasked.  Finer control must be done in the driver/apps.

#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
externC cyg_uint8 cyg_hal_ILVL_table[];
#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_)                         \
    /* Update the ILVL table, so it is easy for the interrupt entry */   \
    /* code to find out the level of a given interrupt source.      */   \
    cyg_hal_ILVL_table[(_vector_)] = (_level_)
#else
#define HAL_UPDATE_ILVL_TABLE(_vector_, _level_)
#endif

#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )                     \
    CYG_MACRO_START                                                      \
    cyg_uint16 iprX;                                                     \
                                                                         \
    CYG_ASSERT((0 <= (_level_) && 15 >= (_level_)), "Illegal level");    \
    CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (_vector_)                         \
                && CYGNUM_HAL_ISR_MAX >= (_vector_)), "Illegal vector"); \
                                                                         \
    HAL_UPDATE_ILVL_TABLE(_vector_, _level_);                            \
                                                                         \
    switch( (_vector_) ) {                                               \
    case CYGNUM_HAL_INTERRUPT_NMI:                                       \
        /* fall through */                                               \
    case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:         \
        /* Cannot change levels */                                       \
        break;                                                           \
                                                                         \
    /* IPRA */                                                           \
    case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0:                                \
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);                          \
        iprX &= ~CYGARC_REG_IPRA_TMU0_MASK;                              \
        iprX |= (_level_)*CYGARC_REG_IPRA_TMU0_PRI1;                     \
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);                         \
        break;                                                           \
    case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1:                                \
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);                          \
        iprX &= ~CYGARC_REG_IPRA_TMU1_MASK;                              \
        iprX |= (_level_)*CYGARC_REG_IPRA_TMU1_PRI1;                     \
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);                         \
        break;                                                           \
    case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2:                                \
    case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2:                               \
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);                          \
        iprX &= ~CYGARC_REG_IPRA_TMU2_MASK;                              \
        iprX |= (_level_)*CYGARC_REG_IPRA_TMU2_PRI1;                     \
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);                         \
        break;                                                           \
    case CYGNUM_HAL_INTERRUPT_RTC_ATI:                                   \
    case CYGNUM_HAL_INTERRUPT_RTC_PRI:                                   \
    case CYGNUM_HAL_INTERRUPT_RTC_CUI:                                   \
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);                          \
        iprX &= ~CYGARC_REG_IPRA_RTC_MASK;                               \
        iprX |= (_level_)*CYGARC_REG_IPRA_RTC_PRI1;                      \
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);                         \
        break;                                                           \
                                                                         \
    /* IPRB */                                                           \
    case CYGNUM_HAL_INTERRUPT_WDT_ITI:                                   \
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);                          \
        iprX &= ~CYGARC_REG_IPRB_WDT_MASK;                               \
        iprX |= (_level_)*CYGARC_REG_IPRB_WDT_PRI1;                      \
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);                         \
        break;                                                           \
    case CYGNUM_HAL_INTERRUPT_REF_RCMI:                                  \
    case CYGNUM_HAL_INTERRUPT_REF_ROVI:                                  \
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);                          \
        iprX &= ~CYGARC_REG_IPRB_REF_MASK;                               \
        iprX |= (_level_)*CYGARC_REG_IPRB_REF_PRI1;                      \
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);                         \
        break;                                                           \
    case CYGNUM_HAL_INTERRUPT_SCI_ERI:                                   \
    case CYGNUM_HAL_INTERRUPT_SCI_RXI:                                   \
    case CYGNUM_HAL_INTERRUPT_SCI_TXI:                                   \
    case CYGNUM_HAL_INTERRUPT_SCI_TEI:                                   \
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);                          \
        iprX &= ~CYGARC_REG_IPRB_SCI_MASK;                               \
        iprX |= (_level_)*CYGARC_REG_IPRB_SCI_PRI1;                      \
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);                         \
        break;                                                           \
                                                                         \
    case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:                              \
    case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:                              \
        /* Do nothing for these reserved vectors. */                     \
        break;                                                           \
    }                                                                    \
    CYG_MACRO_END


#define HAL_INTERRUPT_MASK( _vector_ )                                    \
    CYG_MACRO_START                                                       \
    switch( (_vector_) ) {                                                \
    case CYGNUM_HAL_INTERRUPT_NMI:                                        \
        /* fall through */                                                \
    case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:          \
        /* Can only be masked by fiddling Imask in SR. */                 \
        break;                                                            \
    case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_INTERRUPT_REF_ROVI: \
        HAL_INTERRUPT_SET_LEVEL((_vector_), 0);                           \
        break;                                                            \
    case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:                               \
    case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:                               \
        /* Do nothing for these reserved vectors. */                      \
        break;                                                            \
    default:                                                              \
        CYG_FAIL("Unknown interrupt vector");                             \
        break;                                                            \
    }                                                                     \
    CYG_MACRO_END

#define HAL_INTERRUPT_UNMASK( _vector_ )                                  \
    CYG_MACRO_START                                                       \
    switch( (_vector_) ) {                                                \
    case CYGNUM_HAL_INTERRUPT_NMI:                                        \
        /* fall through */                                                \
    case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:          \
        /* Can only be unmasked by fiddling Imask in SR. */               \
        break;                                                            \
    case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_INTERRUPT_REF_ROVI: \
        HAL_INTERRUPT_SET_LEVEL((_vector_), 1);                           \
        break;                                                            \
    case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:                               \
    case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:                               \
        /* Do nothing for these reserved vectors. */                      \
        break;                                                            \
    default:                                                              \
        CYG_FAIL("Unknown interrupt vector");                             \
        break;                                                            \
    }                                                                     \
    CYG_MACRO_END

#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )

#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )

//--------------------------------------------------------------------------
// Clock control

// Using TMU counter 0, clocked at p/4, with peripheral clock
// sourced directly from the 15MHz crystal (which is the default setup
// on the EDK).  This means 150000/4 oscillations in 1/100 second.
#define HAL_CLOCK_INITIALIZE( _period_ )                                \
    CYG_MACRO_START                                                     \
    register cyg_uint8 _tstr_;                                          \
                                                                        \
    /* Disable timer while programming it. */                           \
    HAL_READ_UINT8(CYGARC_REG_TSTR, _tstr_);                            \
    _tstr_ &= ~CYGARC_REG_TSTR_STR0;                                    \
    HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_);                           \
                                                                        \
    /* Set counter registers. */                                        \
    HAL_WRITE_UINT32(CYGARC_REG_TCOR0, (_period_));                     \
    HAL_WRITE_UINT32(CYGARC_REG_TCNT0, (_period_));                     \
                                                                        \
    /* Set interrupt on underflow, decrement frequency at 1/4 of */     \
    /* peripheral clock.                                         */     \
    HAL_WRITE_UINT16(CYGARC_REG_TCR0, CYGARC_REG_TCR_UNIE);             \
                                                                        \
    /* Enable timer. */                                                 \
    _tstr_ |= CYGARC_REG_TSTR_STR0;                                     \
    HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_);                           \
                                                                        \
    CYG_MACRO_END

#define HAL_CLOCK_RESET( _vector_, _period_ )           \
    CYG_MACRO_START                                     \
    register cyg_uint16 _tcr_;                          \
                                                        \
    /* Clear underflow flag. */                         \
    HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_);            \
    _tcr_ &= ~CYGARC_REG_TCR_UNF;                       \
    HAL_WRITE_UINT16(CYGARC_REG_TCR0, _tcr_);           \
    HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_);            \
                                                        \
    CYG_MACRO_END

#define HAL_CLOCK_READ( _pvalue_ )                              \
    CYG_MACRO_START                                             \
    register cyg_uint32 _result_;                               \
                                                                \
    HAL_READ_UINT32(CYGARC_REG_TCNT0, _result_);                \
                                                                \
    *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-_result_;   \
    CYG_MACRO_END

#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
#endif

#endif // __ASSEMBLER__

//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_INTR_H
// End of hal_intr.h