wireless_usb.vhd

无线耳机通讯用CPLD的VHDL源码

library IEEE;
use IEEE.std_logic_1164.all;
use work.Wireless_USB_pack.all;

entity Wireless_USB is
	port ( 	 
		CLK: in STD_LOGIC;	             				-- 24MHz clock input
		RESET: in STD_LOGIC; 		      				-- Master reset pin (1 = resets logic)
		RD_n: in STD_LOGIC;              	 			-- Controller reads parallel DATA byte (active low)
		WR_n: in STD_LOGIC;                				-- Controller writes parallel DATA byte (active low)	   
--		BIT_RATE: in STD_LOGIC_VECTOR (3 downto 0);
		SERIAL_DATA_IN: in STD_LOGIC;				    -- Asynchronous serial input from RF-Modem receiver 
		SERIAL_DATA_OUT: OUT STD_LOGIC;				 	-- serial data to RF-Modem transmitter 
		RX_TX: in STD_LOGIC;            		      	-- AKA Tx/Rx pin (0 = puts logic to receive mode , 1 = puts logic to transmit mode)
		DATA: inout STD_LOGIC_VECTOR (7 downto 0);	 	-- Parallel DATA byte input/outputs
		BYTE_READY: out STD_LOGIC;      		 	 	-- When '1' logic is ready to transfer byte to the Controller
		LOCKED: out STD_LOGIC;         			 	    -- When goes low, logic detected valid preamble and start bit when goes high, logic is no longer locked on a packet
		TX_EMPTY: out STD_LOGIC;				 	 	-- When '1' logic is ready to accept data for transmittion
		PREAMBLE: in STD_LOGIC_VECTOR (7 downto 0);	 	-- preamble low byte correlation code
		CRC_ENABLE: in std_logic				  	 	--when '1' enable crc calculation in crc block.
	);
end Wireless_USB;

architecture behave of Wireless_USB is
	signal rd, wr : std_logic;
	signal data_out : std_logic_vector (7 downto 0);
	signal tx_serial_out, rx_serial_in	: std_logic;
	signal tx_crc_result_ready: std_logic;
	signal crc_bus : std_logic_vector (15 downto 0);
	signal result_write_en : std_logic;	
	signal crc_result : std_logic_vector (7 downto 0);
	signal crc_ignore : std_logic;	
	
	component RECEIVER 
		port (	  	  
			CLK: in STD_LOGIC;
			RESET: in STD_LOGIC;
			RD : in STD_LOGIC;
			SERIAL_DATA_IN: in STD_LOGIC;
			PARALLEL_DATA_OUT: out STD_LOGIC_VECTOR (7 downto 0);
			RECEIVER_FULL: out STD_LOGIC;
			RECEIVER_LOCKED: out STD_LOGIC;
			PREAMBLE: in STD_LOGIC_VECTOR (7 downto 0)
		);
	end component;
	
	
	component TRANSMITTER 
		port (
		CLK : in std_logic;
		RESET : in std_logic;
		WR : in std_logic;
		PARALLEL_DATA_IN : in std_logic_vector(7 downto 0);
		SERIAL_DATA_OUT : out std_logic;
		TRANSMITTER_EMPTY : out std_logic;
		CRC_READY_TO_TX : in std_logic;
		CRC_WRITE_EN : out std_logic;
		CRC_IN : in std_logic_vector(15 downto 0) 
		);
	end component;
	
	component CRC16 						   
	port (
		DATA: in STD_LOGIC_VECTOR (7 downto 0);
		WR: in STD_LOGIC;
		RD: in STD_LOGIC;	
		ENABLE: in STD_LOGIC;
		WRITE_CRC_EN: in std_logic;			  
		CRC_OUT: buffer STD_LOGIC_VECTOR (15 downto 0);
		RESULT_READY: out std_logic;
		CLK: in STD_LOGIC;
		RX_TX: in STD_LOGIC;
		CRC_RX_RESULT : out STD_LOGIC_VECTOR (7 downto 0);
		IGNORE_DATA: out STD_LOGIC;
		RESET: in STD_LOGIC
	);
	end component; 
	
begin

-- rd_n and wr_n are inverted only to ease writing the code (now they active high)

	wr <= not WR_n;
	rd <= not RD_n; 	
	
--	the DATA is drivven by the receiver data_out and by the crc_result
--  normally it connects to the receiver data_out except for the time that the crc_ignore signal is high
--  meaning that the next two reads are the the crc calculation result and not DATA.
-- the crc_ignore is drivven by the crc block
	
	DATA <= data_out when (rd = '1' and  crc_ignore= '0') else
			crc_result when	(rd = '1' and crc_ignore = '1')else
			("ZZZZZZZZ"); 
			
			
	SERIAL_DATA_OUT <= tx_serial_out when (RX_TX = '1') else 'Z';	

	rx_serial_in <= SERIAL_DATA_IN	when (RX_TX = '0') else '0';
    
			
	tx : TRANSMITTER 
	port map (
		CLK => CLK,
		RESET => RESET,
		WR => wr,
		PARALLEL_DATA_IN => DATA,
		SERIAL_DATA_OUT => tx_serial_out,
		TRANSMITTER_EMPTY => TX_EMPTY,
		CRC_IN => crc_bus,
		CRC_WRITE_EN => result_write_en,
		CRC_READY_TO_TX => tx_crc_result_ready); 
		
	rx : RECEIVER 
	port map (	
		CLK => CLK,
		RESET => RESET,
		RD => rd,
		SERIAL_DATA_IN => rx_serial_in,
		PARALLEL_DATA_OUT => data_out,
		RECEIVER_FULL => BYTE_READY,
		RECEIVER_LOCKED => LOCKED,
		PREAMBLE => PREAMBLE);
	 
	crc : CRC16
	port map (
		CLK => CLK,
		RESET => RESET,
		WR => wr,
		RD => rd,
		ENABLE => CRC_ENABLE,
		RX_TX => RX_TX,
		RESULT_READY =>	tx_crc_result_ready,
		CRC_OUT	=> crc_bus,
		WRITE_CRC_EN => result_write_en,
		CRC_RX_RESULT => crc_result,
		IGNORE_DATA => crc_ignore,
		DATA =>	DATA);
			   
end behave;