wireless_usb_pack.vhd

来自「无线耳机通讯用CPLD的VHDL源码」· VHDL 代码 · 共 15 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package Wireless_USB_pack is

	constant MIN_PULSE_COUNT : integer := 6;			   -- the number of successive logic '1' samples of the serial input bit need to synchronize interval counter 
	constant MAX_PULSE_INTERVAL_COUNT: integer := 16;	   -- the max nunber successive  logic '1' samples of the serial input bit allowed for a valid bit  
	constant PULSE_CLOCK_COUNT : integer := 14;			   -- the number of clocks the serial out bit needs to be at logic '1'
	constant PREAMBLE_CORRELATION_LENGTH : integer := 9;  -- the length of the data correlation vector 
	constant START_BIT : std_logic := '1';				   -- the number S.B for each byte
	constant BIT_INTERVAL : integer := 24;				   -- number of clocks to generate 1 usec timer
end ;