hardware logic - readme.txt

来自「无线耳机通讯用CPLD的VHDL源码」· 文本 代码 · 共 12 行

VHDL Source Code for the RFW102 Hardware Logic Ver- 1.0
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File Structure:
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Top Entity : wireless_usb
Packages : pck_crc16_d8 , wireless_usb_pack.
Modules : receiver , transmitter , crc16