fet430_dac12_04.c

msp430开发c语言例程

//******************************************************************************
//  MSP-FET430P430 Demo - DAC12.0 Output Voltage Ramp  
//
//  Description; Using DAC12.0 and 2.5V ADC12REF reference with a gain of 1, 
//  ouput positive ramp on VeREF. Normal mode is LPM0 with CPU off.  WDT used
//  to provide ~0.061ms interrupt used to wake up the CPU and update the DAC 
//  with software. Use internal 2.5V Vref.  This code example shows how to set
//  the DAC output to the second DAC0 output on the FG devices.
//
//               MSP430FG439
//            -----------------
//        /|\|              XIN|-  
//         | |                 |
//         --|RST          XOUT|-
//           |                 |
//           |       DAC0/VeREF|--> Ramp_positive
//           |                 |
//
//  M.Buccini
//  Texas Instruments, Inc
//  June 2004
//  Built with IAR Embedded Workbench Version: 2.21B
//******************************************************************************

#include  <msp430xG43x.h>

void main(void)
{ 
  WDTCTL = WDT_MDLY_0_064;              // WDT ~0.061ms interval timer
  IE1 = WDTIE;                          // Enable WDT interrupt 
  ADC12CTL0 = REF2_5V + REFON;          // Internal 2.5V ref on 
  DAC12_0CTL = DAC12IR + DAC12AMP_5 + DAC12ENC + DAC12OPS; // Internal ref gain
                                                       // of 1, output on VeREF
  _EINT();                              // Enable interrupts
  
  for (;;)                              
  {
    _BIS_SR(CPUOFF);                    // Enter LPM0
    DAC12_0DAT++;                       // Positive ramp
    DAC12_0DAT &= 0xFFF;                //     
  }
}

#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer (void)
{
    _BIC_SR_IRQ(CPUOFF);                // Clear LPM0 bits from 0(SR)
}