fet430_tb05.c

msp430开发c语言例程

//******************************************************************************
//  MSP-FET430P430 Demo - Timer_B Toggle P5.1, TBCCR0 upmode ISR, 32kHz ACLK 
//
//  Description; Toggle P5.1 using software and the TB_0 ISR. Timer_B is 
//  configured in an upmode, thus the the timer will overflow when TBR counts 
//  to TBCCR0. In this example, TBCCR0 is loaded with 1000-1.
//  Toggle rate = 32768/(2*1000) = 16.384 Hz
//  ACLK = TBCLK = LFXT1 = 32768, MCLK = SMCLK = DCO = 32xACLK = 1.048576MHz
//  //*An external watch crystal on XIN XOUT is required for ACLK*//	  
//   
//           MSP430FG439
//         ---------------
//     /|\|            XIN|-  
//      | |               | 32kHz
//      --|RST        XOUT|-
//        |               |
//        |           P5.1|-->LED
//
//  M. Buccini
//  Texas Instruments, Inc
//  June 2004
//  Built with IAR Embedded Workbench Version: 2.21B
//******************************************************************************

#include <msp430xG43x.h>

void main(void)
{ 
  WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
  FLL_CTL0 |= XCAP14PF;                 // Configure load caps
  P5DIR |= 0x02;                        // Set P5.1 to output direction
  TBCCTL0 = CCIE;                       // TRCCR0 interrupt enabled
  TBCCR0 = 1000-1;
  TBCTL = TBSSEL_1 + MC_1;              // ACLK, upmode
 
  _BIS_SR(LPM3_bits + GIE);             // Enter LPM3 w/ interrupt
}

// Timer B0 interrupt service routine
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B (void)
{
    P5OUT ^= 0x02;                      // Toggle P5.1 using exclusive-OR
}