fet430_tb01.c

msp430开发c语言例程

//******************************************************************************
//  MSP-FET430P430 Demo - Timer_B Toggle P5.1, TBCCR0 Contmode ISR, DCO SMCLK 
//
//  Description; Toggle P5.1 using software and TB_0 ISR. Toggle rate is 
//  set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TBCLK. 
//  During the TB_0 ISR, P5.1 is toggled and 50000 clock cycles are added to 
//  CCR0.  TB_0 ISR is triggered exactly 50000 cycles. CPU is normally off and
//  used only during TB_ISR. 
//  ACLK = n/a, MCLK = SMCLK = TBCLK = DCO = 32xACLK = 1.048576Mhz
//
//           MSP430FG439
//         ---------------
//     /|\|            XIN|-  
//      | |               |
//      --|RST        XOUT|-
//        |               |
//        |           P5.1|-->LED
//
//  M.Buccini
//  Texas Instruments, Inc
//  June 2004
//  Built with IAR Embedded Workbench Version: 2.21B
//******************************************************************************

#include <msp430xG43x.h>

void main(void)
{ 
  WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
  P5DIR |= 0x02;                        // P5.1 output
  TBCCTL0 = CCIE;                       // CCR0 interrupt enabled
  TBCCR0 = 50000;
  TBCTL = TBSSEL_2 + MC_2;              // SMCLK, contmode

  _BIS_SR(LPM0_bits + GIE);             // Enter LPM0 w/ interrupt
}

// Timer B0 interrupt service routine
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B (void)
{
  P5OUT ^= 0x02;                        // Toggle P5.1
  TBCCR0 += 50000;                      // Add Offset to CCR0
}