lmc_var.h

hdlc wan 驱动程序

        u_int32_t       version_size;
        u_int32_t       lmc_cardtype;

        u_int32_t       tx_ProcTimeout;
        u_int32_t       tx_IntTimeout;
        u_int32_t       tx_NoCompleteCnt;
        u_int32_t       tx_MaxXmtsB4Int;
        u_int32_t       tx_TimeoutCnt;
        u_int32_t       tx_OutOfSyncPtr;
        u_int32_t       tx_tbusy0;
        u_int32_t       tx_tbusy1;
        u_int32_t       tx_tbusy_calls;
        u_int32_t       resetCount;
        u_int32_t       lmc_txfull;
        u_int32_t       tbusy;
        u_int32_t       dirtyTx;
        u_int32_t       lmc_next_tx;
        u_int32_t       otherTypeCnt;
        u_int32_t       lastType;
        u_int32_t       lastTypeOK;
        u_int32_t       txLoopCnt;
        u_int32_t       usedXmtDescripCnt;
        u_int32_t       txIndexCnt;
        u_int32_t       rxIntLoopCnt;

        u_int32_t       rx_SmallPktCnt;
        u_int32_t       rx_BadPktSurgeCnt;
        u_int32_t       rx_BuffAllocErr;
        u_int32_t       tx_lossOfClockCnt;

        /* T1 error counters */
        u_int32_t       framingBitErrorCount;
        u_int32_t       lineCodeViolationCount;

        u_int32_t       lossOfFrameCount;
        u_int32_t       changeOfFrameAlignmentCount;
        u_int32_t       severelyErroredFrameCount;

        u_int32_t       check;
};


typedef struct lmc_xinfo {
        u_int32_t       Magic0;                         /* BEEFCAFE */

        u_int32_t       PciCardType;
        u_int32_t       PciSlotNumber;          /* PCI slot number       */

        u_int16_t       DriverMajorVersion;
        u_int16_t       DriverMinorVersion;
        u_int16_t       DriverSubVersion;

        u_int16_t       XilinxRevisionNumber;
        u_int16_t       MaxFrameSize;

        u_int16_t       t1_alarm1_status;
        u_int16_t       t1_alarm2_status;

        int                     link_status;
        u_int32_t       mii_reg16;

        u_int32_t       Magic1;                         /* DEADBEEF */
} LMC_XINFO;


/*
 * forward decl
 */
struct lmc___softc {
        void *if_ptr;   /* General purpose pointer (used by SPPP) */
	char                   *name;
	u8			board_idx;
	struct lmc_statistics   stats;
	struct net_device          *lmc_device;

	int                     hang, rxdesc, bad_packet, some_counter;
	u_int32_t               txgo;
	struct lmc_regfile_t	lmc_csrs;
	volatile u_int32_t	lmc_txtick;
	volatile u_int32_t	lmc_rxtick;
	u_int32_t		lmc_flags;
	u_int32_t		lmc_intrmask;	/* our copy of csr_intr */
	u_int32_t		lmc_cmdmode;	/* our copy of csr_cmdmode */
	u_int32_t		lmc_busmode;	/* our copy of csr_busmode */
	u_int32_t		lmc_gpio_io;	/* state of in/out settings */
	u_int32_t		lmc_gpio;	/* state of outputs */
	struct sk_buff*		lmc_txq[LMC_TXDESCS];
	struct sk_buff*		lmc_rxq[LMC_RXDESCS];
	volatile
	struct tulip_desc_t	lmc_rxring[LMC_RXDESCS];
	volatile
	struct tulip_desc_t	lmc_txring[LMC_TXDESCS];
	unsigned int		lmc_next_rx, lmc_next_tx;
	volatile
	unsigned int		lmc_taint_tx, lmc_taint_rx;
	int			lmc_tx_start, lmc_txfull;
	int			lmc_txbusy;
	u_int16_t		lmc_miireg16;
	int			lmc_ok;
	int			last_link_status;
	int			lmc_cardtype;
	u_int32_t               last_frameerr;
	lmc_media_t	       *lmc_media;
	struct timer_list	timer;
	lmc_ctl_t		ictl;
	u_int32_t		TxDescriptControlInit;  

	int                     tx_TimeoutInd; /* additional driver state */
	int                     tx_TimeoutDisplay;
	unsigned int		lastlmc_taint_tx;
	int                     lasttx_packets;
	u_int32_t		tx_clockState;
	u_int32_t		lmc_crcSize;
	LMC_XINFO		lmc_xinfo; 
	char                    lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
        char                    lmc_timing; /* for HSSI and SSI */
        int                     got_irq;

        char                    last_led_err[4];

        u32                     last_int;
        u32                     num_int;

	spinlock_t              lmc_lock;
        u_int16_t               if_type;       /* PPP or NET */
        struct ppp_device       *pd;

        /* Failure cases */
        u8                       failed_ring;
        u8                       failed_recv_alloc;

        /* Structure check */
        u32                     check;
};

#define LMC_PCI_TIME 1
#define LMC_EXT_TIME 0

#define PKT_BUF_SZ              1542  /* was 1536 */

/* CSR5 settings */
#define TIMER_INT     0x00000800
#define TP_LINK_FAIL  0x00001000
#define TP_LINK_PASS  0x00000010
#define NORMAL_INT    0x00010000
#define ABNORMAL_INT  0x00008000
#define RX_JABBER_INT 0x00000200
#define RX_DIED       0x00000100
#define RX_NOBUFF     0x00000080
#define RX_INT        0x00000040
#define TX_FIFO_UNDER 0x00000020
#define TX_JABBER     0x00000008
#define TX_NOBUFF     0x00000004
#define TX_DIED       0x00000002
#define TX_INT        0x00000001

/* CSR6 settings */
#define OPERATION_MODE  0x00000200 /* Full Duplex      */
#define PROMISC_MODE    0x00000040 /* Promiscuous Mode */
#define RECIEVE_ALL     0x40000000 /* Recieve All      */
#define PASS_BAD_FRAMES 0x00000008 /* Pass Bad Frames  */

/* Dec control registers  CSR6 as well */
#define LMC_DEC_ST 0x00002000
#define LMC_DEC_SR 0x00000002

/* CSR15 settings */
#define RECV_WATCHDOG_DISABLE 0x00000010
#define JABBER_DISABLE        0x00000001

/* More settings */
/*
 * aSR6 -- Command (Operation Mode) Register
 */
#define TULIP_CMD_RECEIVEALL    0x40000000L /* (RW)  Receivel all frames? */
#define TULIP_CMD_MUSTBEONE     0x02000000L /* (RW)  Must Be One (21140) */
#define TULIP_CMD_TXTHRSHLDCTL  0x00400000L /* (RW)  Transmit Threshold Mode (21140) */
#define TULIP_CMD_STOREFWD      0x00200000L /* (RW)  Store and Foward (21140) */
#define TULIP_CMD_NOHEARTBEAT   0x00080000L /* (RW)  No Heartbeat (21140) */
#define TULIP_CMD_PORTSELECT    0x00040000L /* (RW)  Post Select (100Mb) (21140) */
#define TULIP_CMD_FULLDUPLEX    0x00000200L /* (RW)  Full Duplex Mode */
#define TULIP_CMD_OPERMODE      0x00000C00L /* (RW)  Operating Mode */
#define TULIP_CMD_PROMISCUOUS   0x00000041L /* (RW)  Promiscuous Mode */
#define TULIP_CMD_PASSBADPKT    0x00000008L /* (RW)  Pass Bad Frames */
#define TULIP_CMD_THRESHOLDCTL  0x0000C000L /* (RW)  Threshold Control */

#define TULIP_GP_PINSET         0x00000100L
#define TULIP_BUSMODE_SWRESET   0x00000001L
#define TULIP_WATCHDOG_TXDISABLE 0x00000001L
#define TULIP_WATCHDOG_RXDISABLE 0x00000010L

#define TULIP_STS_NORMALINTR    0x00010000L /* (RW)  Normal Interrupt */
#define TULIP_STS_ABNRMLINTR    0x00008000L /* (RW)  Abnormal Interrupt */
#define TULIP_STS_ERI           0x00004000L /* (RW)  Early Receive Interrupt */
#define TULIP_STS_SYSERROR      0x00002000L /* (RW)  System Error */
#define TULIP_STS_GTE           0x00000800L /* (RW)  General Pupose Timer Exp */
#define TULIP_STS_ETI           0x00000400L /* (RW)  Early Transmit Interrupt */
#define TULIP_STS_RXWT          0x00000200L /* (RW)  Receiver Watchdog Timeout */
#define TULIP_STS_RXSTOPPED     0x00000100L /* (RW)  Receiver Process Stopped */
#define TULIP_STS_RXNOBUF       0x00000080L /* (RW)  Receive Buf Unavail */
#define TULIP_STS_RXINTR        0x00000040L /* (RW)  Receive Interrupt */
#define TULIP_STS_TXUNDERFLOW   0x00000020L /* (RW)  Transmit Underflow */
#define TULIP_STS_TXJABER       0x00000008L /* (RW)  Jabber timeout */
#define TULIP_STS_TXNOBUF       0x00000004L
#define TULIP_STS_TXSTOPPED     0x00000002L /* (RW)  Transmit Process Stopped */
#define TULIP_STS_TXINTR        0x00000001L /* (RW)  Transmit Interrupt */

#define TULIP_STS_RXS_STOPPED   0x00000000L /*        000 - Stopped */

#define TULIP_STS_RXSTOPPED     0x00000100L             /* (RW)  Receive Process Stopped */
#define TULIP_STS_RXNOBUF       0x00000080L

#define TULIP_CMD_TXRUN         0x00002000L /* (RW)  Start/Stop Transmitter */
#define TULIP_CMD_RXRUN         0x00000002L /* (RW)  Start/Stop Receive Filtering */
#define TULIP_DSTS_TxDEFERRED   0x00000001      /* Initially Deferred */
#define TULIP_DSTS_OWNER        0x80000000      /* Owner (1 = 21040) */
#define TULIP_DSTS_RxMIIERR     0x00000008
#define LMC_DSTS_ERRSUM         (TULIP_DSTS_RxMIIERR)

#define TULIP_DEFAULT_INTR_MASK  (TULIP_STS_NORMALINTR \
  | TULIP_STS_RXINTR       \
  | TULIP_STS_TXINTR     \
  | TULIP_STS_ABNRMLINTR \
  | TULIP_STS_SYSERROR   \
  | TULIP_STS_TXSTOPPED  \
  | TULIP_STS_TXUNDERFLOW\
  | TULIP_STS_RXSTOPPED )

#define DESC_OWNED_BY_SYSTEM   ((u_int32_t)(0x00000000))
#define DESC_OWNED_BY_DC21X4   ((u_int32_t)(0x80000000))

#ifndef TULIP_CMD_RECEIVEALL
#define TULIP_CMD_RECEIVEALL 0x40000000L
#endif

/* Adapter module number */
#define LMC_ADAP_HSSI           2
#define LMC_ADAP_DS3            3
#define LMC_ADAP_SSI            4
#define LMC_ADAP_T1             5

#define HDLC_HDR_LEN  4
#define HDLC_ADDR_LEN 1
#define HDLC_SLARP    0x8035
#define LMC_MTU 1500
#define SLARP_LINECHECK 2

#define LMC_CRC_LEN_16 2  /* 16-bit CRC */
#define LMC_CRC_LEN_32 4

#ifdef LMC_HDLC
/* definition of an hdlc header. */
struct hdlc_hdr
{
	u8  address;
	u8  control;
	u16 type;
};

/* definition of a slarp header. */
struct slarp
{
	long code;
	union sl
	{
		struct
		{
			ulong address;
			ulong mask;
			ushort unused;
		} add;
		struct
		{
			ulong mysequence;
			ulong yoursequence;
			ushort reliability;
			ulong time;
		} chk;
	} t;
};
#endif /* LMC_HDLC */


#endif /* _LMC_VAR_H_ */