add_beh.v

加法器,加法器描述

/*********************************************************/
// MODULE:		adder
//
// FILE NAME:	add_beh.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Behavioral Level
//
// DESCRIPTION:	This module defines an adder with
// synchronous add enable and reset inputs. When the adder
// is synchronously reset, the outputs go to zero and the
// valid signal is asserted on the next clock cycle. When
// the add enable input is asserted and the valid output is
// asserted during the same clock cycle, the adder begins
// adding. When the valid output signal is again asserted
// on a subsequent clock cycle, the new output is correct.
// Note that the inputs must be held steady from the cycle
// during which the add enable input is asserted until the
// cycle during which the valid output signal is asserted.
//
/*********************************************************/

// DEFINES
`define DEL	1			// Clock-to-output delay. Zero
						// time delays can be confusing
						// and sometimes cause problems.
`define BITS 32			// Bit width of the operands

// TOP MODULE
module Adder(
		clk,
		a,
		b,
		reset_n,
		add_en,
		out,
		cout,
		valid);

// INPUTS
input				clk;		// Clock
input [`BITS-1:0]	a;			// Operand A input
input [`BITS-1:0]	b;			// Operand B input
input				reset_n;	// Active low, synchronous reset
input				add_en;		// Synchronous add enable control

// OUTPUTS
output [`BITS-1:0]	out;		// Output
output				cout;		// Carry output
output				valid;		// Is the output valid yet?

// INOUTS

// SIGNAL DECLARATIONS
wire				clk;
wire [`BITS-1:0]	a;
wire [`BITS-1:0]	b;
wire				reset_n;
wire				add_en;
reg  [`BITS-1:0]	out;
reg					cout;
reg					valid;

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Look for the reset_n signal
always @(reset_n) begin
	// if reset gets deasserted, unforce the output
	if (reset_n) begin
		deassign out;
		deassign cout;
		cout = 1'b0;
		out = `BITS'h0;
	end
	// Wait for the rising edge of the clock
	@(posedge clk);
	// If reset is asserted at the clock, force the output
	// to the current input value (delayed by `DEL)
	if (~reset_n) begin
		#`DEL
		assign cout = 1'b0;
		assign out = `BITS'h0;
	end
end

// Look at the rising edge of the clock
always @(posedge clk) begin
	if (add_en)
		{cout, out} <= #`DEL a+b;

	// Output is valid after reset or add operation
	// And remains valid forever
	valid <= #`DEL ~reset_n | add_en | valid;
end
endmodule		// Adder