📄 4510b_cstartup.hdr
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; 0x2=3Cycle, 0x3=4Cycle
rTacc4 EQU (0x4<<4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON4 DEFINE ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
;---------------------------------------------------------------
;---------------------------------------------------------------
; 设置ROMCON5寄存器:ROM Bank5 Control register
ROMBasePtr5 EQU 0x170<<10 ; =0x1700000
ROMEndPtr5 EQU 0x180<<20 ; =0x1800000
PMC5 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa5 EQU (0x0<<2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc5 EQU (0x4<<4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON5 DEFINE ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
;---------------------------------------------------------------
;---------------------------------------------------------------
; 设置DRAMCON0寄存器:RAM Bank0 control register
EDO_Mode0 EQU 1 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime0 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime0 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON0Reserved EQU 1 ; Must be set to 1
RAS2CASDelay0 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime0 EQU 2 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr0 EQU 0x000<<10 ;=0x0000000 16M BYTE
DRAMEndPtr0 EQU 0x100<<20 ;=0x1000000
NoColumnAddr0 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;---------------------------------------------------------------
Tcs0 EQU CasStrobeTime0<<1
Tcp0 EQU CasPrechargeTime0<<3
dumy0 EQU DRAMCON0Reserved<<4 ; dummy cycle
Trc0 EQU RAS2CASDelay0<<7
Trp0 EQU RASPrechargeTime0<<8
CAN0 EQU NoColumnAddr0<<30
rDRAMCON0 DEFINE CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
;---------------------------------------------------------------
SRAS2CASDelay0 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime0 EQU 3 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr0 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN0 EQU SNoColumnAddr0<<30
STrc0 EQU SRAS2CASDelay0<<7
STrp0 EQU SRASPrechargeTime0<<8
rSDRAMCON0 DEFINE SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0;0x10000380
;---------------------------------------------------------------
;---------------------------------------------------------------
; 设置DRAMCON1寄存器:RAM Bank1 control register
EDO_Mode1 EQU 1 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime1 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime1 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON1Reserved EQU 0 ; Must be set to 1
RAS2CASDelay1 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime1 EQU 0 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr1 EQU 0x200<<10 ;=0x2000000
DRAMEndPtr1 EQU 0x210<<20 ;=0x2100000
NoColumnAddr1 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;---------------------------------------------------------------
Tcs1 EQU CasStrobeTime1<<1
Tcp1 EQU CasPrechargeTime1<<3
dumy1 EQU DRAMCON1Reserved<<4 ; dummy cycle
Trc1 EQU RAS2CASDelay1<<7
Trp1 EQU RASPrechargeTime1<<8
CAN1 EQU NoColumnAddr1<<30
rDRAMCON1 DEFINE CAN1+DRAMEndPtr1+DRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
;---------------------------------------------------------------
SRAS2CASDelay1 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime1 EQU 1 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr1 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN1 EQU SNoColumnAddr1<<30
STrc1 EQU SRAS2CASDelay1<<7
STrp1 EQU SRASPrechargeTime1<<8
rSDRAMCON1 DEFINE SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+STrc1;0x00000000
;---------------------------------------------------------------
;---------------------------------------------------------------
; 设置DRAMCON2寄存器:RAM Bank2 control register
EDO_Mode2 EQU 0 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime2 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime2 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON2Reserved EQU 1 ; Must be set to 1
RAS2CASDelay2 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime2 EQU 0 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr2 EQU 0x210<<10 ;=0x2100000
DRAMEndPtr2 EQU 0x220<<20 ;=0x2200000
NoColumnAddr2 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;---------------------------------------------------------------
Tcs2 EQU CasStrobeTime2<<1
Tcp2 EQU CasPrechargeTime2<<3
dumy2 EQU DRAMCON2Reserved<<4 ; dummy cycle
Trc2 EQU RAS2CASDelay2<<7
Trp2 EQU RASPrechargeTime2<<8
CAN2 EQU NoColumnAddr2<<30
rDRAMCON2 DEFINE CAN2+DRAMEndPtr2+DRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
;---------------------------------------------------------------
SRAS2CASDelay2 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime2 EQU 1 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr2 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN2 EQU SNoColumnAddr2<<30
STrc2 EQU SRAS2CASDelay2<<7
STrp2 EQU SRASPrechargeTime2<<8
rSDRAMCON2 DEFINE SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+STrc2;0x00000000
;---------------------------------------------------------------
;---------------------------------------------------------------
; 设置DRAMCON3寄存器:RAM Bank3 control register
EDO_Mode3 EQU 0 ;(EDO)0=Normal, 1=EDO DRAM
CasPrechargeTime3 EQU 0 ;(Tcp)0=1cycle,1=2cycle
CasStrobeTime3 EQU 1 ;(Tcs)0=1cycle ~ 3=4cycle
DRAMCON3Reserved EQU 1 ; Must be set to 1
RAS2CASDelay3 EQU 0 ;(Trc)0=1cycle,1=2cycle
RASPrechargeTime3 EQU 0 ;(Trp)0=1cycle ~ 3=4clcyle
DRAMBasePtr3 EQU 0x220<<10 ;=0x2200000
DRAMEndPtr3 EQU 0x230<<20 ;=0x2300000
NoColumnAddr3 EQU 2 ;0=8bit,1=9bit,2=10bit,3=11bits
;---------------------------------------------------------------
Tcs3 EQU CasStrobeTime3<<1
Tcp3 EQU CasPrechargeTime3<<3
dumy3 EQU DRAMCON3Reserved<<4 ; dummy cycle
Trc3 EQU RAS2CASDelay3<<7
Trp3 EQU RASPrechargeTime3<<8
CAN3 EQU NoColumnAddr3<<30
rDRAMCON3 DEFINE CAN3+DRAMEndPtr3+DRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
;---------------------------------------------------------------
SRAS2CASDelay3 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime3 EQU 1 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr3 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN3 EQU SNoColumnAddr3<<30
STrc3 EQU SRAS2CASDelay3<<7
STrp3 EQU SRASPrechargeTime3<<8
rSDRAMCON3 DEFINE SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+STrc3;0x00000000
;---------------------------------------------------------------
;---------------------------------------------------------------
; 设置REFEXTCON寄存器:External I/O & Memory Refresh cycle Control Register
MHz EQU 1000000
fMCLK_MHz EQU 50000000
fMCLK EQU fMCLK_MHz/MHz
RefCycle EQU 16 ;Unit [us], 1k refresh 16ms
CASSetupTime EQU 0 ;0=1cycle, 1=2cycle
CASHoldTime EQU 0 ;0=1cycle, 1=2cycle, 2=3cycle,
;3=4cycle, 4=5cycle,
RefCycleValue EQU ((2048+1-(RefCycle*fMCLK))<<21)
Tcsr EQU (CASSetupTime<<20) ; 1cycle
Tcs EQU (CASHoldTime<<17)
ExtIOBase EQU 0x18360 ; Refresh enable, VSF=1
rREFEXTCON DEFINE RefCycleValue+Tcsr+Tcs+ExtIOBase
;---------------------------------------------------------------
;SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
SRefCycle EQU 8 ;Unit [us], 4k refresh 64ms
ROWcycleTime EQU 3 ;0=1cycle, 1=2cycle, 2=3cycle,
;3=4cycle, 4=5cycle,
SRefCycleValue EQU ((2048+1-(SRefCycle*fMCLK))<<21)
STrc EQU (ROWcycleTime<<17)
rSREFEXTCON DEFINE SRefCycleValue+STrc+ExtIOBase;0x9C518360
;---------------------------------------------------------------⌨️ 快捷键说明
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