📄 egaint10.inc
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;***
; EGAINT10 - Source for EGAINT10 driver
;***
.XLIST
;***
;
; Copyright <C> 1986, Microsoft Corporation
;
;Purpose:
; This driver for the EGAINT10 interface allows the EGA registers
; to be read as well as written. It is loaded only if a valid
; EGA.SYS or MOUSE.SYS driver containing the interface is not
; detected during initialization.
;
;******************************************************************************
;
; SCCSID = @(#)egaint10.inc 5.6 87/06/23
;-----------------------------------------------------------------------------;
; brian conte 12/24/84 ;
; egaint10.inc v1.40 ;
; steve shaiman (mod to RevertDefault for glitch in 11/11/85 ;
; in graphics controller misc. register) v1.50 ;
; steve shaiman (mod to ChangeRegs to clear the direction 2/14/86 ;
; flag instead of assuming it's cleared) v1.51 ;
; steve shaiman (made Int10Vector, ChangeRegs, Int10Routine 2/21/86 ;
; public as needed by erice) v1.52 ;
; steve shaiman (mod to RevertDefault for glitch in 6/09/86 ;
; in sequencer clocking mode register) v1.53 ;
; steve shaiman (added GetDefault as function f8) 10/30/86 ;
; (added SimWriteReg & SimWriteSet for use v1.60 ;
; by routines that intercept standard Int 10 ;
; calls and want to modify the shadow regs ;
; but not the actual hardware regs) ;
; (added int 10h bios support for functions ;
; 5 [set display page], b [set CGA palette ;
; registers] & 10 [set EGA palette registers] ;
; jtp (fixed bug in SetEgaPalette to split 17-byte 4/01/87 ;
; update into two updates) ;
; jtp (incorporated various bug fixes, primarily to ;
; SetCgaPalette and SetEgaPalette Int hooks) 4/12/87 ;
; jtp (optimized Int10Routine to minimize time ;
; spent on ignored functions, and optimized ;
; the rep-movsw's in the egaint10 functions) 4/12/87 ;
; jtp (added kludge to RevertDefault to update ;
; Bios data areas too, for Word /C operation) 5/24/87 ;
; ;
; egaint10 is an interface to the ega card which allows all of the w/o ;
; registers to be read from as well as written to. this is a requirement ;
; in order to use interrupt-driven graphics (such as cursor update code). ;
; interrupt-driven graphics can be implemented on the ega if both the ;
; synchronous app and the interrupt code use the egaint10 interface ;
; to the ega registers. the microsoft mouse driver (version 3.0 and ;
; greater) uses the egaint10 interface to the ega card. ;
; ;
; this file contains the code that intercepts the int 10's and keeps ;
; shadow maps of all ega registers so that these registers can be ;
; read as well as written. note that the primary consideration was ;
; speed, some of the calls need to be made in tight graphics loops. for ;
; this reason, the interface may seem arbitrary and the code may seem ;
; unnecessarily "tricky" at time. i've tried to document all such ;
; instances. also keep in mind that there is no error checking of ;
; parameters. illegal parameters may cause unpredictable results, ;
; including possibly a system crash. ;
; ;
; this code may be used in a standalone driver, or may be incorporated ;
; into an app or another driver if desired. here are the requirements ;
; for using this code: ;
; ;
; include the file inside your code segment. ;
; ;
; put the current screen mode in ah, and bits 7:4 of the ;
; crtc io address ("b" for "3b4", "d" for "3d4) into bits 7:4 ;
; of al, set ds to zero, and then call "ChangeRegs". ;
; ;
; get the current int 10 vector and save it in "Int10Vector". ;
; ;
; set the int 10 vector to point to cs:Int10Routine. ;
; ;
; after this, regular int 10 and extended int 10 calls may ;
; be executed as desired. ;
; ;
; the code that does this in the ega.sys standalone driver follows: ;
; ;
; xor ax,ax ;
; mov ds,ax ;
; mov ah,ds:[449h] ;
; mov al,byte ptr ds:[463h] ;
; and al,11110000b ;
; call ChangeRegs ;
; mov ax,cs ;
; mov ds,ax ;
; assume ds:Code ;
; mov ax,3510h ;
; int 21h ;
; mov word ptr [Int10Vector],bx ;
; mov word ptr [Int10Vector+2],es ;
; mov ax,2510h ;
; mov dx,offset Int10Routine ;
; int 21h ;
; ;
; eventually ega.sys will intercept all bios calls and update its tables. ;
; right now it only intercepts calls to set the mode (ah=0). ;
; ;
; ega.sys is reentrant. this means that it is legal for an interrupt ;
; routine to call ega.sys while the synchronous program is in the middle of ;
; one of its calls to ega.sys. [currently, this is only true if the ;
; interrupt routine only saves and restores registers (ie makes no permanent;
; changes) but this could be changed to accomodate interrupt routines that ;
; make permanent changes (eg an interrupt routine that changed the palette ;
; on a vertical retrace).] ;
; ;
; a special note about the attribute chip registers: the flip-flop which ;
; determines whether 3c0 is the address or data register must be set to ;
; "address" before making extended int 10 calls. it will always be left ;
; in the "address" state on return. interrupt code must be sure to set ;
; the flip flop to "address" before using attribute registers, and to ;
; return it to "address" on return. any code which sets the flip flop ;
; to "data" and then depends on it being set that way must disable ;
; interrupts for the length of time between setting it to "data" and the ;
; last time it is assumed to be "data". ;
; ;
; this code knows nothing about the sequencer memory mode register. this ;
; is because the sequencer will produce a 20 ns glitch on the cas lines ;
; when this register is accessed, which seems to have a chance of glitching ;
; vram even though write enable is never asserted. therefore, reading to ;
; or writing to this register using these routines is an error. ;
; ;
; this code does not restore the contents of the graphics controller ;
; miscellaneous register as part of the RevertDefault (function F6). ;
; this is because it appears to cause a glitch on the cas lines in a ;
; similar to the sequencer memory mode register. the rest of the code ;
; does not give this register any special treatment, and it is the ;
; responsibility of the programmer to be careful. this problem is ;
; particularly insideous because it will only show up on EGA cards with ;
; the add on memory cards that have INMOS RAM chips. Beware!!! ;
; ;
; this code has no provisions for reading the input status registers ;
; on the ega. any code that wants to read either of the input status ;
; registers should do so directly. ;
; ;
; extended int 10 call interface spec: ;
; ;
; Read One Register ;
; ;
; in: ah 0f0h ;
; dx: port number ;
; 0h: crtc chip (3x4h) ;
; 8h: sequencer chip (3c4h) ;
; 10h: graphics chips (3ceh) ;
; 18h: attribute chip (3c0h) ;
; 20h: misc out reg (3c2h) ;
; 28h: feature reg (3xah) ;
; 30h: gr 1 pos reg (3cch) ;
; 38h: gr 2 pos reg (3cah) ;
; bx: ptr for ptr/data ports (first 4 above) (bh=0, bl=ptr);
; ignored for single registers (last 4 above) ;
; ;
; return: ax restored ;
; bl data ;
; bh restored ;
; dx restored ;
; all others restored ;
; ;
; ;
; Write One Register ;
; ;
; in: ah 0f1h ;
; dx port number ;
; 0h: crtc chip (3x4h) ;
; 8h: sequencer chip (3c4h) ;
; 10h: graphics chips (3ceh) ;
; 18h: attribute chip (3c0h) ;
; 20h: misc out reg (3c2h) ;
; 28h: feature reg (3xah) ;
; 30h: gr 1 pos reg (3cch) ;
; 38h: gr 2 pos reg (3cah) ;
; bl pointer value for ptr/data ports (first 4 above) ;
; data for single registers (last 4 above) ;
; bh data for ptr/data ports ;
; ignored for single registers ;
; ;
; return: ax restored ;
; bl restored ;
; bh trashed ;
; dx trashed ;
; all others restored ;
; ;
; ;
; Read Register Range ;
; ;
; in: ah 0f2h ;
; dx port number ;
; 0h: crtc chip (3x4h) ;
; 8h: sequencer chip (3c4h) ;
; 10h: graphics chips (3ceh) ;
; 18h: attribute chip (3c0h) ;
; es:bx table of values ;
; ch starting pointer value ;
; cl number of regs (must be > 1) ;
; ;
; return: ax restored ;
; bx restored ;
; cx trashed ;
; dx restored ;
; es restored ;
; all others restored ;
; ;
; ;
; Write Register Range ;
; ;
; in: ah 0f3h ;
; dx port number ;
; 0h: crtc chip (3x4h) ;
; 8h: sequencer chip (3c4h) ;
; 10h: graphics chips (3ceh) ;
; 18h: attribute chip (3c0h) ;
; es:bx table of values ;
; ch starting pointer value ;
; cl number of regs (must be > 1) ;
; ;
; return: ax restored ;
; bx trashed ;
; dx trashed ;
; es restored ;
; all others restored ;
; ;
; ;
; Read Register Set ;
; ;
; in: ah 0f4h ;
; es:bx table of values, where each entry consists of ;
; port number (word) ;
; pointer value (byte) (should be 0 for ;
; single registers) ;
; data (byte) ;
; cx number of regs (must be > 1) ;
; ;
; return: ax restored ;
; bx restored ;
; cx trashed ;
; es restored ;
; all others restored ;
; ;
; ;
; Write Register Set ;
; ;
; in: ah 0f5h ;
; es:bx table of values, where each entry consists of ;
; port number (word) ;
; pointer value (byte) (should be 0 for ;
; single registers) ;
; data (byte) ;
; cx number of regs (must be > 1) ;
; ;
; return: ax restored ;
; bx restored ;
; cx trashed ;
; es restored ;
; all others restored ;
; ;
; Revert To Default Registers ;
; ;
; in: ah 0f6h ;
; ;
; return: all registers restored ;
; ;
; ;
; Define Default Register Table ;
; ;
; in: ah 0f7h ;
; dx port number ;
; 0h: crtc chip (3x4h) ;
; 8h: sequencer chip (3c4h) ;
; 10h: graphics chips (3ceh) ;
; 18h: attribute chip (3c0h) ;
; 20h: misc out reg (3c2h) ;
; 28h: feature reg (3xah) ;
; 30h: gr 1 pos reg (3cch) ;
; 38h: gr 2 pos reg (3cah) ;
; es:bx points to table of default values (all must be present);
; ;
; return: ax restored ;
; bx trashed ;
; dx trashed ;
; es restored ;
; all others restored ;
; ;
; ;
; Get Default Register Table ;
; ;
; in: ah 0f8h ;
; dx port number ;
; 0h: crtc chip (3x4h) ;
; 8h: sequencer chip (3c4h) ;
; 10h: graphics chips (3ceh) ;
; 18h: attribute chip (3c0h) ;
; 20h: misc out reg (3c2h) ;
; 28h: feature reg (3xah) ;
; 30h: gr 1 pos reg (3cch) ;
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