smc91x.h

LUBBOCK板的BLOB

/*------------------------------------------------------------------------
 . smc91x.h - macros for the LAN91C111 Ethernet Driver
 .
 . (C) Copyright 2002
 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 . Rolf Offermanns <[e-mail]>
 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
 .       Developed by Simple Network Magic Corporation (SNMC)
 . Copyright (C) 1996 by Erik Stahlman (ES)
 .
 . This program is free software; you can redistribute it and/or modify
 . it under the terms of the GNU General Public License as published by
 . the Free Software Foundation; either version 2 of the License, or
 . (at your option) any later version.
 .
 . This program is distributed in the hope that it will be useful,
 . but WITHOUT ANY WARRANTY; without even the implied warranty of
 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 . GNU General Public License for more details.
 .
 . You should have received a copy of the GNU General Public License
 . along with this program; if not, write to the Free Software
 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 .
 . This file contains register information and access macros for 
 . the LAN91C111 single chip ethernet controller.  It is a modified
 . version of the smc9194.h file.
 . 
 . Information contained in this file was obtained from the LAN91C111
 . manual from SMC.  To get a copy, if you really want one, you can find 
 . information under www.smsc.com.
 . 
 . Authors
 . 	Erik Stahlman				( [e-mail] )
 .	Daris A Nevil				( [e-mail] )
 .
 . History
 . 03/16/01		Daris A Nevil	Modified for use with LAN91C111 device
 .
 ---------------------------------------------------------------------------*/
#ifndef _SMC91X_H_
#define _SMC91X_H_

/*
 * This function may be called by the board specific initialisation code
 * in order to override the default mac address.
 */

void smc_set_mac_addr(const char *addr);

/* I want some simple types */

typedef unsigned char			byte;
typedef unsigned short			word;
typedef unsigned long int 		dword;

/*
 . DEBUGGING LEVELS
 .
 . 0 for normal operation
 . 1 for slightly more details
 . >2 for various levels of increasingly useless information
 .    2 for interrupt tracking, status flags
 .    3 for packet info
 .    4 for complete packet dumps
*/
//#define SMC_DEBUG 0

/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */

#define	SMC_IO_EXTENT	16

/* 
 * IO routines 
 */

#if defined(CPU_pxa250) || defined(CPU_pxa255) || defined(CPU_pxa262)

#define CONFIG_SMC91X_BASE  ( 0x0C000000 )

#define readw(p) ({ \
		volatile u16 * __p = (volatile u16*)(p); \
		*__p; \
		})
#define writew(val, p) ({ \
		volatile u16 * __p = (volatile u16*)(p); \
		*__p = val; \
		})

static inline u8 SMC_inb(u32 reg)
{
	u32 base = CONFIG_SMC91X_BASE;
	u32 port = base + (reg & ~1) * 4;
	u16 res = readw(port);
	if (reg & 1)
		res >>= 8;
	return res;
}

static inline u16 SMC_inw(u32 reg)
{
	u32 base = CONFIG_SMC91X_BASE;
	u32 port = base + reg * 4;
	return readw(port);
}


static inline void SMC_outb(u8 val, u32 reg)
{
	u32 base = CONFIG_SMC91X_BASE;
	u32 port = base + (reg & ~1) * 4;
	u16 res = readw(port);
	if (reg & 1) {
		res &= 0xff;
		res |= val << 8;
	} else {
		res &= 0xff00;
		res |= val;
	}
	writew(res, port);
}

static inline void SMC_outw(u16 val, u32 reg)
{
	u32 base = CONFIG_SMC91X_BASE;
	u32 port = base + reg * 4;
	writew(val, port);
}

static inline void SMC_outl(u32 val,  u32 reg)
{
	u32 base = CONFIG_SMC91X_BASE;
	u32 port = base + reg * 4;
	writew(val, port);
	writew(val >> 16, port + 8);
}

inline 
void SMC_insb(u32 addr, u8 *buf, int ns)
{
	int i;
	u8 *p=buf;
	for(i= 0; i< ns; i++) {
		p[i] = SMC_inb(addr);
	}
}

inline 
void SMC_insw(u32 addr, u8 *buf, int ns)
{
	int i;
	u16 *p=(u16*)buf;
	for(i= 0; i< ns; i++) {
		p[i] = SMC_inw(addr);
	}
}

inline 
void SMC_outsw(u32 addr, u8 *buf, int ns)
{
	int i;
	u16 *p = (u16*)buf;

	for(i= 0; i< ns; i++) {
		SMC_outw(p[i], addr);
	}
}

#else /* if not pxa250/pxa255/pxa262 */


/*
 * We have only 16 Bit PCMCIA access on Socket 0
 */

#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
#define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)

#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
				word __w = SMC_inw((r)&~1);  \
				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
				__w |= ((r)&1) ? __d<<8 : __d;  \
				SMC_outw(__w,(r)&~1);  \
			})
#if 0
#define	SMC_outsw(r,b,l)	outsw(SMC_BASE_ADDRESS+(r), (b), (l))
#else
#define SMC_outsw(r,b,l)	({	int __i; \
					word *__b2; \
					__b2 = (word *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outw( *(__b2 + __i), r); \
					} \
				})
#endif

#if 0
#define	SMC_insw(r,b,l) 	insw(SMC_BASE_ADDRESS+(r), (b), (l))
#else
#define SMC_insw(r,b,l) 	({	int __i ;  \
					word *__b2;  \
			    		__b2 = (word *) b;  \
			    		for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inw(r);  \
					  SMC_inw(0);  \
					};  \
				})
#endif

#endif

/*---------------------------------------------------------------
 .  
 . A description of the SMSC registers is probably in order here,
 . although for details, the SMC datasheet is invaluable.  
 . 
 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
 . are accessed by writing a number into the BANK_SELECT register
 . ( I also use a SMC_SELECT_BANK macro for this ).
 . 
 . The banks are configured so that for most purposes, bank 2 is all
 . that is needed for simple run time tasks.  
 -----------------------------------------------------------------------*/

/*
 . Bank Select Register: 
 .
 .		yyyy yyyy 0000 00xx  
 .		xx 		= bank number
 .		yyyy yyyy	= 0x33, for identification purposes.
*/
#define	BANK_SELECT		14

// Transmit Control Register
/* BANK 0  */
#define	TCR_REG 	0x0000 	// transmit control register 
#define TCR_ENABLE	0x0001	// When 1 we can transmit
#define TCR_LOOP	0x0002	// Controls output pin LBK
#define TCR_FORCOL	0x0004	// When 1 will force a collision
#define TCR_PAD_EN	0x0080	// When 1 will pad tx frames < 64 bytes w/0
#define TCR_NOCRC	0x0100	// When 1 will not append CRC to tx frames
#define TCR_MON_CSN	0x0400	// When 1 tx monitors carrier
#define TCR_FDUPLX    	0x0800  // When 1 enables full duplex operation
#define TCR_STP_SQET	0x1000	// When 1 stops tx if Signal Quality Error
#define	TCR_EPH_LOOP	0x2000	// When 1 enables EPH block loopback
#define	TCR_SWFDUP	0x8000	// When 1 enables Switched Full Duplex mode

#define	TCR_CLEAR	0	/* do NOTHING */
/* the default settings for the TCR register : */ 
/* QUESTION: do I want to enable padding of short packets ? */
#define	TCR_DEFAULT  	TCR_ENABLE


// EPH Status Register
/* BANK 0  */
#define EPH_STATUS_REG	0x0002
#define ES_TX_SUC	0x0001	// Last TX was successful
#define ES_SNGL_COL	0x0002	// Single collision detected for last tx
#define ES_MUL_COL	0x0004	// Multiple collisions detected for last tx
#define ES_LTX_MULT	0x0008	// Last tx was a multicast
#define ES_16COL	0x0010	// 16 Collisions Reached
#define ES_SQET		0x0020	// Signal Quality Error Test
#define ES_LTXBRD	0x0040	// Last tx was a broadcast
#define ES_TXDEFR	0x0080	// Transmit Deferred
#define ES_LATCOL	0x0200	// Late collision detected on last tx
#define ES_LOSTCARR	0x0400	// Lost Carrier Sense
#define ES_EXC_DEF	0x0800	// Excessive Deferral
#define ES_CTR_ROL	0x1000	// Counter Roll Over indication
#define ES_LINK_OK	0x4000	// Driven by inverted value of nLNK pin
#define ES_TXUNRN	0x8000	// Tx Underrun


// Receive Control Register
/* BANK 0  */
#define	RCR_REG		0x0004
#define	RCR_RX_ABORT	0x0001	// Set if a rx frame was aborted
#define	RCR_PRMS	0x0002	// Enable promiscuous mode
#define	RCR_ALMUL	0x0004	// When set accepts all multicast frames
#define RCR_RXEN	0x0100	// IFF this is set, we can receive packets
#define	RCR_STRIP_CRC	0x0200	// When set strips CRC from rx packets
#define	RCR_ABORT_ENB	0x0200	// When set will abort rx on collision 
#define	RCR_FILT_CAR	0x0400	// When set filters leading 12 bit s of carrier
#define RCR_SOFTRST	0x8000 	// resets the chip

/* the normal settings for the RCR register : */
#define	RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
#define RCR_CLEAR	0x0	// set it to a base state

// Counter Register
/* BANK 0  */
#define	COUNTER_REG	0x0006

// Memory Information Register
/* BANK 0  */
#define	MIR_REG		0x0008

// Receive/Phy Control Register
/* BANK 0  */
#define	RPC_REG		0x000A
#define	RPC_SPEED	0x2000	// When 1 PHY is in 100Mbps mode.
#define	RPC_DPLX	0x1000	// When 1 PHY is in Full-Duplex Mode
#define	RPC_ANEG	0x0800	// When 1 PHY is in Auto-Negotiate Mode
#define	RPC_LSXA_SHFT	5	// Bits to shift LS2A,LS1A,LS0A to lsb
#define	RPC_LSXB_SHFT	2	// Bits to get LS2B,LS1B,LS0B to lsb
#define RPC_LED_100_10	(0x00)	// LED = 100Mbps OR's with 10Mbps link detect
#define RPC_LED_RES	(0x01)	// LED = Reserved
#define RPC_LED_10	(0x02)	// LED = 10Mbps link detect
#define RPC_LED_FD	(0x03)	// LED = Full Duplex Mode
#define RPC_LED_TX_RX	(0x04)	// LED = TX or RX packet occurred
#define RPC_LED_100	(0x05)	// LED = 100Mbps link dectect
#define RPC_LED_TX	(0x06)	// LED = TX packet occurred
#define RPC_LED_RX	(0x07)	// LED = RX packet occurred
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100_10 << RPC_LSXA_SHFT) | (RPC_LED_RX << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)

/* Bank 0 0x000C is reserved */

// Bank Select Register
/* All Banks */
#define BSR_REG	0x000E


// Configuration Reg
/* BANK 1 */
#define CONFIG_REG	0x0000
#define CONFIG_EXT_PHY	0x0200	// 1=external MII, 0=internal Phy
#define CONFIG_GPCNTRL	0x0400	// Inverse value drives pin nCNTRL
#define CONFIG_NO_WAIT	0x1000	// When 1 no extra wait states on ISA bus
#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.

// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
#define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)