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📄 network_main.asm

📁 DSP图像采集程序源代码
💻 ASM
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;*      Register Usage Table:
;*          +-----------------------------------------------------------------+
;*          |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;*          |00000000001111111111222222222233|00000000001111111111222222222233|
;*          |01234567890123456789012345678901|01234567890123456789012345678901|
;*          |--------------------------------+--------------------------------|
;*       0: |*  * **                         |*                               |
;*          +-----------------------------------------------------------------+
;*
;*      Done
;*
;*      Collapsed epilog stages     : 11
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 11 bytes
;*      Minimum threshold value     : -mh14
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*       SETUP CODE
;*
;*                  MVK             0x1,B0
;*                  ZERO            A6
;*
;*        SINGLE SCHEDULED ITERATION
;*
;*        C91:
;*   0              LDB     .D1T1   *++A3,A0          ; |175|  ^ 
;*   1              NOP             3
;*   4              ADD     .L1     1,A5,A5           ; |175|  ^ 
;*   5      [ B0]   MV      .S1     A5,A6             ; |175|  ^ 
;*       || [!A0]   ZERO    .D2     B0                ;  ^ 
;*   6      [ B0]   B       .S2     C91               ; |175| 
;*   7              NOP             5
;*                  ; BRANCH OCCURS                   ; |175| 
;*
;*       RESTORE CODE
;*
;*                  MV              A6,A5
;*----------------------------------------------------------------------------*
L2:    ; PIPED LOOP PROLOG
           LDB     .D1T1   *++A3,A0          ; |175| (P) <1,0>  ^ 
           LDB     .D1T1   *++A3,A0          ; |175| (P) <2,0>  ^ 
           LDB     .D1T1   *++A3,A0          ; |175| (P) <3,0>  ^ 

           MVK     .D2     0x1,B0
||         ZERO    .S1     A6
||         ADD     .L1     1,A5,A5           ; |175| (P) <0,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <4,0>  ^ 

   [!A0]   ZERO    .D2     B0                ; (P) <0,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <0,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <1,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <5,0>  ^ 

   [ B0]   B       .S2     L3                ; |175| (P) <0,6> 
|| [!A0]   ZERO    .D2     B0                ; (P) <1,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <1,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <2,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <6,0>  ^ 

   [!A0]   ZERO    .D2     B0                ; (P) <2,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <2,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <3,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <7,0>  ^ 
|| [ B0]   B       .S2     L3                ; |175| (P) <1,6> 

   [ B0]   B       .S2     L3                ; |175| (P) <2,6> 
|| [!A0]   ZERO    .D2     B0                ; (P) <3,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <3,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <4,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <8,0>  ^ 

   [!A0]   ZERO    .D2     B0                ; (P) <4,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <4,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <5,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <9,0>  ^ 
|| [ B0]   B       .S2     L3                ; |175| (P) <3,6> 

   [ B0]   B       .S2     L3                ; |175| (P) <4,6> 
|| [!A0]   ZERO    .D2     B0                ; (P) <5,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <5,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <6,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <10,0>  ^ 

;** --------------------------------------------------------------------------*
L3:    ; PIPED LOOP KERNEL

   [ B0]   B       .S2     L3                ; |175| <5,6> 
|| [!A0]   ZERO    .D2     B0                ; <6,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| <6,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| <7,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| <11,0>  ^ 

;** --------------------------------------------------------------------------*
L4:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*

           MVK     .D1     0xffffffff,A8     ; |172| 
||         MVKL    .S1     _HostName,A3      ; |173| 
||         MVK     .S2     64,B5             ; |176| 

           MV      .D1     A8,A5             ; |172| 
||         MVKH    .S1     _HostName,A3      ; |173| 
||         CMPLTU  .L2X    A6,B5,B0          ; |176| 

   [!B0]   B       .S2     L18               ; |176| 
           MVC     .S2     B4,CSR            ; interrupts on

   [ B0]   LDW     .D1T1   *A3,A7            ; |173| 
|| [!B0]   MVKL    .S1     _printf,A3        ; |80| 

           NOP             1
   [!B0]   MVKH    .S1     _printf,A3        ; |80| 
           NOP             1
           ; BRANCH OCCURS                   ; |176| 
;** --------------------------------------------------------------------------*
           MVC     .S2     CSR,B4

           AND     .D2     -2,B4,B5
||         SUB     .D1     A7,1,A3           ; |173| 

           MVC     .S2     B5,CSR            ; interrupts off
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <0,0>  ^ 

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 175
;*      Loop opening brace source line   : 175
;*      Loop closing brace source line   : 175
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 1
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     0        1*    
;*      .D units                     1*       0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1*       0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          2        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             0        1*    
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 1  Schedule found with 12 iterations in parallel
;*
;*      Register Usage Table:
;*          +-----------------------------------------------------------------+
;*          |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;*          |00000000001111111111222222222233|00000000001111111111222222222233|
;*          |01234567890123456789012345678901|01234567890123456789012345678901|
;*          |--------------------------------+--------------------------------|
;*       0: |*  * **                         |*                               |
;*          +-----------------------------------------------------------------+
;*
;*      Done
;*
;*      Collapsed epilog stages     : 11
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 11 bytes
;*      Minimum threshold value     : -mh14
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*       SETUP CODE
;*
;*                  MVK             0x1,B0
;*                  ZERO            A6
;*
;*        SINGLE SCHEDULED ITERATION
;*
;*        C69:
;*   0              LDB     .D1T1   *++A3,A0          ; |175|  ^ 
;*   1              NOP             3
;*   4              ADD     .L1     1,A5,A5           ; |175|  ^ 
;*   5      [ B0]   MV      .S1     A5,A6             ; |175|  ^ 
;*       || [!A0]   ZERO    .D2     B0                ;  ^ 
;*   6      [ B0]   B       .S2     C69               ; |175| 
;*   7              NOP             5
;*                  ; BRANCH OCCURS                   ; |175| 
;*
;*       RESTORE CODE
;*
;*                  MV              A6,A5
;*----------------------------------------------------------------------------*
L5:    ; PIPED LOOP PROLOG
           LDB     .D1T1   *++A3,A0          ; |175| (P) <1,0>  ^ 
           LDB     .D1T1   *++A3,A0          ; |175| (P) <2,0>  ^ 

           ZERO    .S1     A6
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <3,0>  ^ 

           MVK     .D2     0x1,B0
||         SUB     .S1     A7,1,A7           ; |173| 
||         ADD     .L1     1,A5,A5           ; |175| (P) <0,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <4,0>  ^ 

   [!A0]   ZERO    .D2     B0                ; (P) <0,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <0,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <1,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <5,0>  ^ 

   [ B0]   B       .S2     L6                ; |175| (P) <0,6> 
|| [!A0]   ZERO    .D2     B0                ; (P) <1,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <1,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <2,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <6,0>  ^ 

   [!A0]   ZERO    .D2     B0                ; (P) <2,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <2,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <3,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <7,0>  ^ 
|| [ B0]   B       .S2     L6                ; |175| (P) <1,6> 

   [ B0]   B       .S2     L6                ; |175| (P) <2,6> 
|| [!A0]   ZERO    .D2     B0                ; (P) <3,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <3,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <4,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <8,0>  ^ 

   [!A0]   ZERO    .D2     B0                ; (P) <4,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <4,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <5,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <9,0>  ^ 
|| [ B0]   B       .S2     L6                ; |175| (P) <3,6> 

   [ B0]   B       .S2     L6                ; |175| (P) <4,6> 
|| [!A0]   ZERO    .D2     B0                ; (P) <5,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| (P) <5,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| (P) <6,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| (P) <10,0>  ^ 

;** --------------------------------------------------------------------------*
L6:    ; PIPED LOOP KERNEL

   [ B0]   B       .S2     L6                ; |175| <5,6> 
|| [!A0]   ZERO    .D2     B0                ; <6,5>  ^ 
|| [ B0]   MV      .S1     A5,A6             ; |175| <6,5>  ^ 
||         ADD     .L1     1,A5,A5           ; |175| <7,4>  ^ 
||         LDB     .D1T1   *++A3,A0          ; |175| <11,0>  ^ 

;** --------------------------------------------------------------------------*
L7:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*

           MV      .D1     A8,A5             ; |172| 
||         MV      .L1     A7,A3             ; |173| 
||         MVK     .S1     0x40,A7           ; |176| 

           NOP             2
           MVC     .S2     B4,CSR            ; interrupts on
           CMPLTU  .L1     A6,A7,A0          ; |176| 
   [!A0]   BNOP    .S2     L18,2             ; |176| 
   [!A0]   MVKL    .S1     _printf,A3        ; |80| 
   [!A0]   MVKH    .S1     _printf,A3        ; |80| 
           NOP             1
           ; BRANCH OCCURS                   ; |176| 
;** --------------------------------------------------------------------------*
           MVC     .S2     CSR,B4
           AND     .D2     -2,B4,B5

           LDB     .D1T1   *++A3,A0          ; |175| (P) <0,0>  ^ 
||         MVC     .S2     B5,CSR            ; interrupts off

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line                 : 175
;*      Loop opening brace source line   : 175
;*      Loop closing brace source line   : 175
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 1
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     0        1*    
;*      .D units                     1*       0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     

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