📄 dm642init.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Thu Dec 16 15:46:41 2004 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Large *
;* Calls to RTS : Far *
;* Pipelining : Enabled *
;* Speculative Load : Enabled *
;* Memory Aliases : Presume not aliases (optimistic) *
;* Debug Info : No Debug Info *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.sect ".cinit"
.align 8
.field IR_1,32
.field _LinkStr+0,32
.field SL1,32 ; _LinkStr[0] @ 0
.field SL2,32 ; _LinkStr[1] @ 32
.field SL3,32 ; _LinkStr[2] @ 64
.field SL4,32 ; _LinkStr[3] @ 96
.field SL5,32 ; _LinkStr[4] @ 128
IR_1: .set 20
.sect ".text"
_LinkStr: .usect ".far",20,8
_bMacAddr: .usect ".far",8,8
; d:\ti\c6000\cgtools\bin\opt6x.exe -t -DI0 -v6400 -q -O3 D:\DOCUME~1\ZGL~1.LEG\LOCALS~1\Temp\TI3444_2 D:\DOCUME~1\ZGL~1.LEG\LOCALS~1\Temp\TI3444_5 -w D:/ti/boards/tds642evm/examples/video_networking/jpeg_netcam/obj/
.sect ".text"
.global _dm642_init
;******************************************************************************
;* FUNCTION NAME: _dm642_init *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte *
;******************************************************************************
_dm642_init:
;** --------------------------------------------------------------------------*
MVKL .S1 0x1848200,A3 ; |350|
MVKH .S1 0x1848200,A3 ; |350|
LDW .D1T1 *A3,A3 ; |350|
MVKL .S2 0x1848200,B5 ; |350|
MVKL .S2 0x1848200,B4 ; |351|
MVKH .S2 0x1848200,B5 ; |350|
MVKH .S2 0x1848200,B4 ; |351|
OR .D1 1,A3,A3 ; |350|
STW .D2T1 A3,*B5 ; |350|
LDW .D2T2 *B4,B4 ; |351|
NOP 3
STW .D2T2 B3,*SP--(8) ; |38|
AND .D2 1,B4,B0 ; |351|
[ B0] B .S1 L4 ; |351|
[!B0] MVKL .S1 0x1848200,A3 ; |351| (P) <0,0>
[!B0] MVKH .S1 0x1848200,A3 ; |351| (P) <0,1>
[ B0] MVKL .S1 0x1848204,A3 ; |350|
|| [!B0] LDW .D1T1 *A3,A4 ; |351| (P) <0,2> ^
[ B0] MVKH .S1 0x1848204,A3 ; |350|
[ B0] LDW .D1T1 *A3,A3 ; |350|
; BRANCH OCCURS ; |351|
;** --------------------------------------------------------------------------*
MVK .D2 0x1,B0
NOP 1
AND .D1 1,A4,A0 ; |351| (P) <0,7> ^
|| MVKL .S1 0x1848200,A3 ; |351| (P) <1,0>
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 351
;* Loop closing brace source line : 351
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 2* 1
;* .D units 1 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 3 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | ** |* |
;* 2: | * |* |
;* 3: | * |* |
;* 4: | * |* |
;* 5: | * |* |
;* 6: | * |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 2
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A4
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C38:
;* 0 MVKL .S1 0x1848200,A3 ; |351|
;* 1 MVKH .S1 0x1848200,A3 ; |351|
;* 2 [ B0] LDW .D1T1 *A3,A4 ; |351| ^
;* 3 NOP 4
;* 7 AND .D1 1,A4,A0 ; |351| ^
;* 8 [ A0] ZERO .D2 B0 ; ^
;* 9 [ B0] B .S2 C38 ; |351|
;* 10 NOP 5
;* ; BRANCH OCCURS ; |351|
;*----------------------------------------------------------------------------*
L1: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L2: ; PIPED LOOP KERNEL
[ A0] ZERO .D2 B0 ; <0,8> ^
|| MVKH .S1 0x1848200,A3 ; |351| <1,1>
[ B0] BNOP .S2 L2,4 ; |351| <0,9>
|| [ B0] LDW .D1T1 *A3,A4 ; |351| <1,2> ^
AND .D1 1,A4,A0 ; |351| <1,7> ^
|| MVKL .S1 0x1848200,A3 ; |351| <2,0>
;** --------------------------------------------------------------------------*
L3: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MVKL .S1 0x1848204,A3 ; |350|
MVKH .S1 0x1848204,A3 ; |350|
LDW .D1T1 *A3,A3 ; |350|
;** --------------------------------------------------------------------------*
L4:
MVKL .S2 0x1848204,B5 ; |350|
MVKL .S2 0x1848204,B4 ; |351|
MVKH .S2 0x1848204,B5 ; |350|
MVKH .S2 0x1848204,B4 ; |351|
OR .D1 1,A3,A3 ; |350|
STW .D2T1 A3,*B5 ; |350|
LDW .D2T2 *B4,B4 ; |351|
NOP 4
AND .D2 1,B4,B0 ; |351|
[ B0] B .S1 L8 ; |351|
[ B0] MVKL .S2 _EVMDM642_init,B4 ; |43|
|| [!B0] MVKL .S1 0x1848204,A3 ; |351| (P) <0,0>
[ B0] MVKH .S2 _EVMDM642_init,B4 ; |43|
|| [!B0] MVKH .S1 0x1848204,A3 ; |351| (P) <0,1>
[!B0] LDW .D1T1 *A3,A4 ; |351| (P) <0,2> ^
NOP 2
; BRANCH OCCURS ; |351|
;** --------------------------------------------------------------------------*
MVK .D2 0x1,B0
MVKL .S1 0x1848204,A3 ; |351| (P) <1,0>
AND .D1 1,A4,A0 ; |351| (P) <0,7> ^
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 351
;* Loop closing brace source line : 351
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 2* 1
;* .D units 1 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 3 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | ** |* |
;* 2: | * |* |
;* 3: | * |* |
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