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📄 jpegmain.asm

📁 DSP图像采集程序源代码
💻 ASM
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;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     2*       1     
;*      .D units                     1        0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1        0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          1        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 7  Schedule found with 3 iterations in parallel
;*
;*      Register Usage Table:
;*          +-----------------------------------------------------------------+
;*          |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;*          |00000000001111111111222222222233|00000000001111111111222222222233|
;*          |01234567890123456789012345678901|01234567890123456789012345678901|
;*          |--------------------------------+--------------------------------|
;*       0: |*  **                           |*                               |
;*       1: |   **                           |*                               |
;*       2: |    *                           |*                               |
;*       3: |    *                           |*                               |
;*       4: |    *                           |*                               |
;*       5: |    *                           |*                               |
;*       6: |    *                           |*                               |
;*          +-----------------------------------------------------------------+
;*
;*      Done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 2
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
;*       SETUP CODE
;*
;*                  MVK             0x1,B0
;*                  ZERO            A4
;*
;*        SINGLE SCHEDULED ITERATION
;*
;*        C19:
;*   0              MVKL    .S1     0x1848204,A3      ; |351| 
;*   1              MVKH    .S1     0x1848204,A3      ; |351| 
;*   2      [ B0]   LDW     .D1T1   *A3,A4            ; |351|  ^ 
;*   3              NOP             4
;*   7              AND     .D1     1,A4,A0           ; |351|  ^ 
;*   8      [ A0]   ZERO    .D2     B0                ;  ^ 
;*   9      [ B0]   B       .S2     C19               ; |351| 
;*  10              NOP             5
;*                  ; BRANCH OCCURS                   ; |351| 
;*----------------------------------------------------------------------------*
L5:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L6:    ; PIPED LOOP KERNEL

   [ A0]   ZERO    .D2     B0                ; <0,8>  ^ 
||         MVKH    .S1     0x1848204,A3      ; |351| <1,1> 

   [ B0]   BNOP    .S2     L6,4              ; |351| <0,9> 
|| [ B0]   LDW     .D1T1   *A3,A4            ; |351| <1,2>  ^ 

           AND     .D1     1,A4,A0           ; |351| <1,7>  ^ 
||         MVKL    .S1     0x1848204,A3      ; |351| <2,0> 

;** --------------------------------------------------------------------------*
L7:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
           MVKL    .S2     _DAT_open,B5      ; |25| 
           MVKH    .S2     _DAT_open,B5      ; |25| 
;** --------------------------------------------------------------------------*
L8:    
           CALL    .S2     B5                ; |25| 
           ADDKPC  .S2     RL4,B3,1          ; |25| 
           MVK     .D1     0x1,A6            ; |25| 
           MVK     .D2     0x3,B4            ; |25| 
           ZERO    .S1     A4                ; |25| 
RL4:       ; CALL OCCURS                     ; |25| 
           MVKL    .S2     0x184200c,B4      ; |368| 
           MVKH    .S2     0x184200c,B4      ; |368| 
           LDW     .D2T2   *B4,B4            ; |368| 
           MVKL    .S1     0x184200c,A3      ; |368| 
           MVKH    .S1     0x184200c,A3      ; |368| 
           ZERO    .D1     A4                ; |360| 
           MVKH    .S1     0x1840000,A4      ; |360| 

           MVKL    .S2     0x1842004,B4      ; |364| 
||         OR      .D2     7,B4,B5           ; |368| 

           STW     .D1T2   B5,*A3            ; |368| 
||         MVKH    .S2     0x1842004,B4      ; |364| 

           LDW     .D2T2   *B4,B4            ; |364| 
           NOP             2
           MVKL    .S1     0x1842004,A3      ; |364| 
           MVKH    .S1     0x1842004,A3      ; |364| 
           OR      .D2     7,B4,B4           ; |364| 

           MVKL    .S1     _ACPY2_6X1X_init,A3 ; |36| 
||         STW     .D1T2   B4,*A3            ; |364| 

           LDW     .D1T1   *A4,A4            ; |360| 
||         MVKH    .S1     _ACPY2_6X1X_init,A3 ; |36| 

           ZERO    .D2     B4                ; |360| 
           CALL    .S2X    A3                ; |36| 
           MVKH    .S2     0x1840000,B4      ; |360| 
           ADDKPC  .S2     RL5,B3,0          ; |36| 
           EXTU    .S1     A4,3,3,A4         ; |360| 
           SET     .S1     A4,29,29,A4       ; |360| 
           STW     .D2T1   A4,*B4            ; |360| 
RL5:       ; CALL OCCURS                     ; |36| 
           MVKL    .S1     _DMAN_init,A3     ; |37| 
           MVKH    .S1     _DMAN_init,A3     ; |37| 
           NOP             1
           CALL    .S2X    A3                ; |37| 
           ADDKPC  .S2     RL6,B3,4          ; |37| 
RL6:       ; CALL OCCURS                     ; |37| 
           MVKL    .S1     _DMAN_setup,A3    ; |38| 
           MVKH    .S1     _DMAN_setup,A3    ; |38| 
           MVKL    .S1     _intHeap,A4       ; |38| 

           MVKH    .S1     _intHeap,A4       ; |38| 
||         CALL    .S2X    A3                ; |38| 

           LDW     .D1T1   *A4,A4            ; |38| 
           ADDKPC  .S2     RL7,B3,3          ; |38| 
RL7:       ; CALL OCCURS                     ; |38| 
           MVKL    .S2     _CHAN_init,B4     ; |41| 
           MVKH    .S2     _CHAN_init,B4     ; |41| 
           CALL    .S2     B4                ; |41| 
           ADDKPC  .S2     RL8,B3,4          ; |41| 
RL8:       ; CALL OCCURS                     ; |41| 
           MVKL    .S1     _ICC_init,A3      ; |42| 
           MVKH    .S1     _ICC_init,A3      ; |42| 
           NOP             1
           CALL    .S2X    A3                ; |42| 
           ADDKPC  .S2     RL9,B3,4          ; |42| 
RL9:       ; CALL OCCURS                     ; |42| 
           MVKL    .S1     _SCOM_init,A3     ; |43| 
           MVKH    .S1     _SCOM_init,A3     ; |43| 
           NOP             1
           CALL    .S2X    A3                ; |43| 
           ADDKPC  .S2     RL10,B3,4         ; |43| 
RL10:      ; CALL OCCURS                     ; |43| 
           MVKL    .S2     _intHeap,B4       ; |46| 
           MVKH    .S2     _intHeap,B4       ; |46| 

           MVKL    .S1     _CHAN_setup,A3    ; |46| 
||         LDW     .D2T2   *B4,B5            ; |46| 

           MVKL    .S2     _extHeap,B4       ; |46| 
||         MVKH    .S1     _CHAN_setup,A3    ; |46| 

           MVKH    .S2     _extHeap,B4       ; |46| 
           CALL    .S2X    A3                ; |46| 
           LDW     .D2T2   *B4,B4            ; |46| 
           MV      .D1X    B5,A4             ; |46| 
           MVK     .L2     0x1,B6            ; |46| 
           ZERO    .S1     A8                ; |46| 

           ZERO    .D2     B8                ; |46| 
||         MV      .D1X    B5,A6             ; |46| 
||         ADDKPC  .S2     RL11,B3,0         ; |46| 

RL11:      ; CALL OCCURS                     ; |46| 
           MVKL    .S1     _UTL_setLogs,A3   ; |49| 
           MVKH    .S1     _UTL_setLogs,A3   ; |49| 
           MVKL    .S1     _trace,A4         ; |49| 
           CALL    .S2X    A3                ; |49| 
           MVKH    .S1     _trace,A4         ; |49| 
           MV      .D1     A4,A6             ; |49| 
           MV      .D2X    A4,B6             ; |49| 
           MV      .D2X    A4,B4             ; |49| 
           ADDKPC  .S2     RL12,B3,0         ; |49| 
RL12:      ; CALL OCCURS                     ; |49| 
           MVKL    .S2     _tskVideoInputInit,B4 ; |51| 
           MVKH    .S2     _tskVideoInputInit,B4 ; |51| 
           CALL    .S2     B4                ; |51| 
           ADDKPC  .S2     RL13,B3,4         ; |51| 
RL13:      ; CALL OCCURS                     ; |51| 
           MVKL    .S2     _tskVideoOutputInit,B4 ; |52| 
           MVKH    .S2     _tskVideoOutputInit,B4 ; |52| 
           CALL    .S2     B4                ; |52| 
           ADDKPC  .S2     RL14,B3,4         ; |52| 
RL14:      ; CALL OCCURS                     ; |52| 
;** --------------------------------------------------------------------------*
           MVKL    .S2     _EVMDM642_rset,B5 ; |54| 
           MVKH    .S2     _EVMDM642_rset,B5 ; |54| 
           CALL    .S2     B5                ; |54| 
           MVK     .S2     0x20,B4           ; |54| 
           ADDKPC  .S2     RL15,B3,2         ; |54| 
           MVK     .S1     0x10,A4           ; |54| 
RL15:      ; CALL OCCURS                     ; |54| 
           MVKL    .S1     _EVMDM642_rset,A3 ; |55| 
           MVKH    .S1     _EVMDM642_rset,A3 ; |55| 
           MVK     .S1     0x10,A4           ; |55| 
           CALL    .S2X    A3                ; |55| 
           MVK     .D2     0x8,B4            ; |55| 
           ADDKPC  .S2     RL16,B3,3         ; |55| 
RL16:      ; CALL OCCURS                     ; |55| 
           MVKL    .S2     _EVMDM642_rget,B4 ; |56| 
           MVKH    .S2     _EVMDM642_rget,B4 ; |56| 
           CALL    .S2     B4                ; |56| 
           MVK     .S1     0x13,A4           ; |56| 
           ADDKPC  .S2     RL17,B3,3         ; |56| 
RL17:      ; CALL OCCURS                     ; |56| 
           EXTU    .S1     A4,25,31,A0       ; |56| 
   [ A0]   BNOP    .S1     L10,1             ; |56| 
           MVK     .S1     0x40,A10          ; |56| 
   [ A0]   MVKL    .S1     _tskVideoInputStart,A3 ; |58| 

   [!A0]   MVKL    .S2     _EVMDM642_rget,B4 ; |56| 
|| [ A0]   MVKH    .S1     _tskVideoInputStart,A3 ; |58| 

   [!A0]   MVKH    .S2     _EVMDM642_rget,B4 ; |56| 
           ; BRANCH OCCURS                   ; |56| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*      Disqualified loop: Loop contains a call
;*----------------------------------------------------------------------------*
L9:    
           CALL    .S2     B4                ; |56| 
           ADDKPC  .S2     RL18,B3,3         ; |56| 

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