ezusb.h

linux下的jtag调试软件

xdata volatile BYTE at	0x7FD4	 SUDPTRH  	;
xdata volatile BYTE at	0x7FD5	 SUDPTRL  	;
xdata volatile BYTE at	0x7FD6	 USBCS  	;
xdata volatile BYTE at	0x7FD7	 TOGCTL  	;
xdata volatile BYTE at	0x7FD8	 USBFRAMEL  	;
xdata volatile BYTE at	0x7FD9	 USBFRAMEH  	;
xdata volatile BYTE at	0x7FDA	 SPARE6  	;
xdata volatile BYTE at	0x7FDB	 FNADDR  	;
xdata volatile BYTE at	0x7FDC	 SPARE7  	;
xdata volatile BYTE at	0x7FDD	 USBPAIR  	;
xdata volatile BYTE at	0x7FDE	 IN07VAL  	;
xdata volatile BYTE at	0x7FDF	 OUT07VAL  	;
xdata volatile BYTE at	0x7FE0	 INISOVAL  	;
xdata volatile BYTE at	0x7FE1	 OUTISOVAL  	;
xdata volatile BYTE at	0x7FE2	 FASTXFR  	;
xdata volatile BYTE at	0x7FE3	 AUTOPTRH  	;
xdata volatile BYTE at	0x7FE4	 AUTOPTRL  	;
xdata volatile BYTE at	0x7FE5	 AUTODATA  	;
xdata volatile BYTE at	0x7FE6	 SPARE8  	;
xdata volatile BYTE at	0x7FE7	 SPARE9  	;
xdata volatile BYTE at	0x7FE8	 SETUPDAT[8]  	;
xdata volatile BYTE at	0x7FF0	 OUT8ADDR  	;
xdata volatile BYTE at	0x7FF1	 OUT9ADDR  	;
xdata volatile BYTE at	0x7FF2	 OUT10ADDR  	;
xdata volatile BYTE at	0x7FF3	 OUT11ADDR  	;
xdata volatile BYTE at	0x7FF4	 OUT12ADDR  	;
xdata volatile BYTE at	0x7FF5	 OUT13ADDR  	;
xdata volatile BYTE at	0x7FF6	 OUT14ADDR  	;
xdata volatile BYTE at	0x7FF7	 OUT15ADDR  	;
xdata volatile BYTE at	0x7FF8	 IN8ADDR  	;
xdata volatile BYTE at	0x7FF9	 IN9ADDR  	;
xdata volatile BYTE at	0x7FFA	 IN10ADDR  	;
xdata volatile BYTE at	0x7FFB	 IN11ADDR  	;
xdata volatile BYTE at	0x7FFC	 IN12ADDR  	;
xdata volatile BYTE at	0x7FFD	 IN13ADDR  	;
xdata volatile BYTE at	0x7FFE	 IN14ADDR  	;
xdata volatile BYTE at	0x7FFF	 IN15ADDR  	;



/*-----------------------------------------------------------------------------
	Special Function Registers (sfr at 0xs)
	The byte registers and bits defined in the following list are based
	on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
    If you modify the register definitions below, please regenerate the file
    "ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/

sfr at 0x81 SP		;   // Stack Pointer
sfr at 0x82 DPL		;   // Data Pointer Low
sfr at 0x83 DPH		;		// Data Pointer High
sfr at 0x84 DPL1	;
sfr at 0x85 DPH1	;
sfr at 0x86 DPS		;
	/*  DPS  */
sbit at 0x86 SEL	;


/*  PCON  */
sfr at 0x87 PCON;
sbit at 0x87 IDLE;
sbit at 0x88 STOP;
sbit at 0x89 GF0;
sbit at 0x9A GF1;
sbit at 0x9B SMOD0;

/*  TCON  */
sfr at 0x88 TCON	;
sbit at 0x88 IT0;
sbit at 0x89 IE0;
sbit at 0x8A IT1;
sbit at 0x8B IE1;
sbit at 0x8C TR0;
sbit at 0x8D TF0;
sbit at 0x8E TR1;
sbit at 0x8F TF1;

/*  TMOD  */
sfr at 0x89 TMOD;
	//sbit at 0x M00    = 0x89+0;
	//sbit at 0x M10    = 0x89+1;
	//sbit at 0x CT0    = 0x89+2;
	//sbit at 0x GATE0  = 0x89+3;
	//sbit at 0x M01    = 0x89+4;
	//sbit at 0x M11    = 0x89+5;
	//sbit at 0x CT1    = 0x89+6;
	//sbit at 0x GATE1  = 0x89+7;
sfr at 0x8A TL0;
sfr at 0x8B TL1;
sfr at 0x8C TH0;
sfr at 0x8D TH1;

/*  CKCON  */
sfr at 0x8E CKCON;
sbit at 0x8E MD0;
sbit at 0x8F MD1;
sbit at 0x90 MD2;
sbit at 0x91 T0M;
sbit at 0x92 T1M;
sbit at 0x93 T2M;

sfr at 0x8F SPC_FNC; // Was WRS in Reg320
	/*  CKCON  */
	//sbit at 0x WRS    = 0x8F+0;
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
	/*  EXIF  */
	//sbit at 0x USBINT = 0x91+4;
	//sbit at 0x I2CINT = 0x91+5;
	//sbit at 0x IE4    = 0x91+6;
	//sbit at 0x IE5    = 0x91+7;
sfr at 0x92 MPAGE;

/*  SCON0  */
sfr at 0x98 SCON0;
sbit at 0x98 RI;
sbit at 0x99 TI;
sbit at 0x9A RB8;
sbit at 0x9B TB8;
sbit at 0x9C REN;
sbit at 0x9D SM2;
sbit at 0x9E SM1;
sbit at 0x9F SM0;

sfr at 0x99 SBUF0;
sfr at 0xA8 IE;
	/*  IE  */
	sbit at 0xA8 EX0;
	sbit at 0xA9 ET0;
	sbit at 0xAA EX1;
	sbit at 0xAB ET1;
	sbit at 0xAC ES0;
	sbit at 0xAD ET2;
	sbit at 0xAE ES1;
	sbit at 0xAF EA;

/*  IP  */
sfr at 0xB8 IP;
sbit at 0xB8 PX0;
sbit at 0xB9 PT0;
sbit at 0xBA PX1;
sbit at 0xBB PT1;
sbit at 0xBC PS0;
sbit at 0xBD PT2;
sbit at 0xBE PS1;


sfr at 0xC0 SCON1;
	/*  SCON1  */
	sbit at 0xC0 RI1;
	sbit at 0xC1 TI1;
	sbit at 0xC2 RB81;
	sbit at 0xC3 TB81;
	sbit at 0xC4 REN1;
	sbit at 0xC5 SM21;
	sbit at 0xC6 SM11;
	sbit at 0xC7 SM01;
sfr at 0xC1 SBUF1;
sfr at 0xC8 T2CON;
	/*  T2CON  */
	sbit at 0xC8 CP_RL2;
	sbit at 0xC9 C_T2;
	sbit at 0xCA TR2;
	sbit at 0xCB EXEN2;
	sbit at 0xCC TCLK;
	sbit at 0xCD RCLK;
	sbit at 0xCE EXF2;
	sbit at 0xCF TF2;
sfr at 0xCA RCAP2L;
sfr at 0xCB RCAP2H;
sfr at 0xCC TL2;
sfr at 0xCD TH2;
sfr at 0xD0 PSW;
	/*  PSW  */
	sbit at 0xD0 P;
	sbit at 0xD1 FL;
	sbit at 0xD2 OV;
	sbit at 0xD3 RS0;
	sbit at 0xD4 RS1;
	sbit at 0xD5 F0;
	sbit at 0xD6 AC;
	sbit at 0xD7 CY;
sfr at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
	/*  EICON  */
	sbit at 0xDB INT6;
	sbit at 0xDC RESI;
	sbit at 0xDE ERESI;
	sbit at 0xDF SMOD1;
sfr at 0xE0 ACC;
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
  /*  EIE  */
	sbit at 0xE8 EUSB;
	sbit at 0xE9 EI2C;
	sbit at 0xEA EIEX4;
	sbit at 0xEB EIEX5;
	sbit at 0xEC EIEX6;
sfr at 0xF0 B;
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
  /*  EIP  */
	sbit at 0xF8 PUSB;
	sbit at 0xF9 PI2C;
	sbit at 0xFA EIPX4;
	sbit at 0xFB EIPX5;
	sbit at 0xFC EIPX6;





/*-----------------------------------------------------------------------------
	Bit Masks
-----------------------------------------------------------------------------*/

/* CPU Control & Status Register */
#define bmCLK24OE		bmBIT1
#define bm8052RES		bmBIT0
/* Port Configuration Registers */
/* Port A */
#define bmRXD1OUT		bmBIT7
#define bmRXD0OUT		bmBIT6
#define bmFRD			bmBIT5
#define bmFWR			bmBIT4
#define bmCS			bmBIT3
#define bmOE			bmBIT2
#define bmT1OUT			bmBIT1
#define bmT0OUT			bmBIT0
/* Port B */
#define bmT2OUT			bmBIT7
#define bmINT6			bmBIT6
#define bmINT5			bmBIT5
#define bmINT4			bmBIT4
#define bmTXD1			bmBIT3
#define bmRXD1			bmBIT2
#define bmT2EX			bmBIT1
#define bmT2			bmBIT0
/* Port C */
#define bmRD			bmBIT7
#define bmWR			bmBIT6
#define bmT1			bmBIT5
#define bmT0			bmBIT4
#define bmINT1			bmBIT3
#define bmINT0			bmBIT2
#define bmTXD0			bmBIT1
#define bmRXD0			bmBIT0
/* Isochronous Status & End Point Valid Registers */
#define bmEP15			bmBIT7
#define bmEP14			bmBIT6
#define bmEP13			bmBIT5
#define bmEP12			bmBIT4
#define bmEP11			bmBIT3
#define bmEP10			bmBIT2
#define bmEP9			bmBIT1
#define bmEP8			bmBIT0
/* I2C Control & Status Register */
#define bmSTART			bmBIT7
#define bmSTOP			bmBIT6
#define bmLASTRD		bmBIT5
#define bmID			(bmBIT4 | bmBIT3)
#define bmBERR			bmBIT2
#define bmACK			bmBIT1
#define bmDONE			bmBIT0
/* Interrupt Vector Register */
#define bmIV4			bmBIT6
#define bmIV3			bmBIT5
#define bmIV2			bmBIT4
#define bmIV1			bmBIT3
#define bmIV0			bmBIT2
/* End point Interrupt Request, End Point Interrupt Enable */
/* And End Point Valid Registers */
#define bmEP7			bmBIT7
#define bmEP6			bmBIT6
#define bmEP5			bmBIT5
#define bmEP4			bmBIT4
#define bmEP3			bmBIT3
#define bmEP2			bmBIT2
#define bmEP1			bmBIT1
#define bmEP0			bmBIT0
/* Global Interrupt Request & Enable Registers */
#define bmURES			bmBIT4
#define bmSUSP			bmBIT3
#define bmSUTOK			bmBIT2
#define bmSOF			bmBIT1
#define bmSUDAV			bmBIT0
/* Global Control */
#define bmBREAK			bmBIT3
#define bmBPPULSE		bmBIT2
#define bmBPEN			bmBIT1
#define bmAVEN			bmBIT0
/* USB Control & Status Register */
#define bmRWAKEUP		bmBIT7
#define bmDISCON		bmBIT3
#define bmDISCOE		bmBIT2
#define bmRENUM			bmBIT1
#define bmSIGRESUME		bmBIT0
/* End Point 0 Control & Status Register */
#define bmOUT			bmBIT3
#define bmIN			bmBIT2
#define bmHS			bmBIT1
#define bmHSSTALL		bmBIT0
/* End Point Control & Status Registers */
#define bmEPSTALL		bmBIT0
#define bmEPBUSY		bmBIT1
/* Fast Transfer Register */
#define bmFISO			bmBIT7
#define bmFBLK			bmBIT6
#define bmRPOL			bmBIT5
#define bmRMOD1			bmBIT4
#define bmRMOD0			bmBIT3
#define bmWPOL			bmBIT2
#define bmWMOD1			bmBIT1
#define bmWMOD0			bmBIT0
/* Endpoint Pairing Register */
#define bmISOSEND0		bmBIT7
#define bmPR6OUT		bmBIT5
#define bmPR4OUT		bmBIT4
#define bmPR2OUT		bmBIT3
#define bmPR6IN			bmBIT2
#define bmPR4IN			bmBIT1
#define bmPR2IN			bmBIT0
/* End point control offsets */

/* What is this for? */
enum
{
	IN0BUF_ID = 0,
	IN1BUF_ID,
	IN2BUF_ID,
	IN3BUF_ID,
	IN4BUF_ID,
	IN5BUF_ID,
	IN6BUF_ID,
	IN7BUF_ID,
	OUT0BUF_ID,
	OUT1BUF_ID,
	OUT2BUF_ID,
	OUT3BUF_ID,
	OUT4BUF_ID,
	OUT5BUF_ID,
	OUT6BUF_ID,
	OUT7BUF_ID
};


/* What are these for? */
#define EP0CS	EPIO[0].cntrl
#define IN0BC	EPIO[0].bytes
#define IN1CS	EPIO[1].cntrl
#define IN1BC	EPIO[1].bytes
#define IN2CS	EPIO[2].cntrl
#define IN2BC	EPIO[2].bytes
#define IN3CS	EPIO[3].cntrl
#define IN3BC	EPIO[3].bytes
#define IN4CS	EPIO[4].cntrl
#define IN4BC	EPIO[4].bytes
#define IN5CS	EPIO[5].cntrl
#define IN5BC	EPIO[5].bytes
#define IN6CS	EPIO[6].cntrl
#define IN6BC	EPIO[6].bytes
#define IN7CS	EPIO[7].cntrl
#define IN7BC	EPIO[7].bytes
#define OUT0CS	EPIO[8].cntrl
#define OUT0BC	EPIO[8].bytes
#define OUT1CS	EPIO[9].cntrl
#define OUT1BC	EPIO[9].bytes
#define OUT2CS	EPIO[10].cntrl
#define OUT2BC	EPIO[10].bytes
#define OUT3CS	EPIO[11].cntrl
#define OUT3BC	EPIO[11].bytes
#define OUT4CS	EPIO[12].cntrl
#define OUT4BC	EPIO[12].bytes
#define OUT5CS	EPIO[13].cntrl
#define OUT5BC	EPIO[13].bytes
#define OUT6CS	EPIO[14].cntrl
#define OUT6BC	EPIO[14].bytes
#define OUT7CS	EPIO[15].cntrl
#define OUT7BC	EPIO[15].bytes

#endif