korebot-conf.s

linux下的jtag调试软件

#include "led.S"
#include "pxa250regs.S"
#include "loadreg.S"

.text

.global InitSDRAM
InitSDRAM:

@********************************************************************************************
@** setup memory controller registers
@ ** Dev Manual sect. 5.14 step 1 

@---- Wait 200 usec  
@   ldr r3, =OSCR  @ reset the OS Timer Count to zero
    lreg r3, OSCR
    mov r2, #0  
    str r2, [r3]  
    ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
t1:                
    ldr r2, [r3]  
    cmp r4, r2     
    bgt t1 
    
@    ldr r3, =MSC0       @ Configures /CS0
     lreg r3, MSC0
@    ldr r2, =0x000022C0 @ Generated value
@    lreg r2, 0x000026C0
     lreg r2, 0x26C026C0
     str  r2, [r3] 
     ldr  r2, [r3]      @ the MSC register should be read after it is written with  
                        @ a new value before an access to the memory is attempted. 
                        @ (see MSC section of manual) 
                        @ ** Dev Manual sect. 5.14 step 3 -- (Skip if no SRAM)
    
@    ldr r3, =MDREFR 
    lreg r3, MDREFR 
    ldr r2, [r3]            @ read MDREFR value
@    orr r2, r2, #0x00020000 @ set SDCLK1 = memclk / 2
@    str r2, [r3]            @ configure K2DB1 and K2DB2 
    orr r2, r2, #0x018      @ configure a valid SDRAM Refresh Interval (DRI)
    str r2, [r3]            @ store it 
    orr r2, r2, #0x00010000 @ assert K1RUN for SDCLK1
    str r2, [r3]            @ change from "self-refresh and clock-stop" to "self-refresh" state 
    bic r2, r2, #0x00400000 @ clear SLFRSH bit field
    str r2, [r3]            @ change from "self-refresh" to "Power-down" state 
    orr r2, r2, #0x00008000 @ set the E1PIN bit field
    str r2, [r3]            @ change from "Power-down" to "PWRDNX" state 
    
    nop                     @ no action is required to change from "PWRDNX" to "NOP" state 
                            @ ** Dev Manual sect. 5.14 step 4 -- (Skip if no SDRAM)
@    ldr r3, =MDCNFG         @ Load the SDRAM Configuration register. Must not be enabled yet.
@    ldr r2, =0x00000AC8     @ Generated value
    lreg r3, MDCNFG
    lreg r2, 0x00000AC8
    str r2, [r3]            @ Write to MDCNFG register 
                            @ ** Dev Manual sect. 5.14 step 5 -- (Skip if no SDRAM)
                                                                            
@---- Wait 200 usec
@    ldr r3, =OSCR      @ reset the OS Timer Count to zero
    lreg r3, OSCR
    mov r2, #0 
    str r2, [r3] 
    mov r4, #0x300     @ really 0x2E1 is about 200usec, so 0x300 should be plenty
t2:
    ldr r2, [r3] 
    cmp r4, r2
    bgt t2 
                       @ ** Dev Manual sect. 5.14 step 6 -- (Skip if no SDRAM)
    		       @ make sure the DCACHE is off before step 7
@    mov r0, #0x78      @ turn everything off 
@    mcr p15, 0, r0, c1, c0, 0  @ caches off, MMU off, etc.
                       @ this should not be need if used out of reset. 
                       @ ** Dev Manual sect. 5.14 step 7 -- (Skip if no SDRAM)
@    ldr r3, =0xA0000000 
    mov r3, #0xA0000000 
    mov r2, #8         @ now must do 8 refresh or CBR commands before the first access  

CBR_refresh1:
    str r3, [r3]
    subs r2, r2, #1 
    bne CBR_refresh1 
                       @ ** Dev Manual sect. 5.14 step 8 @ can re-enable DCACHE if it was turned off in step 6 
    
                       @ ** Dev Manual sect. 5.14 step 9
@    ldr r3, =MDCNFG    @ sdram config -- sdram enable 
    lreg r3, MDCNFG
    ldr r2, [r3] 
    orr r2, r2, #0x00000001   @ enable appropriate banks, value depends on selected banks 
    str r2, [r3]              @ write to MDCNFG 
                              @ ** Dev Manual sect. 5.14 step 10 
@    ldr r3, =MDMRS            @ write the MDMRS
@    ldr r2, =0x00020032       @ the writable bits will be written as a 0 
    lreg r3, MDMRS
    lreg r2, 0x00020032
    str r2, [r3] 
                              @ ** Dev Manual sect. 5.14 step 11 (optional)
                              @ (not optional for A0 silicon. This bit must be cleared)
@    ldr r3, =MDREFR           @ enable auto-power-down 
@    ldr r2, [r3] 
@    orr r2, r2, #0x00100000   @ set the APD bit
@    str r2, [r3]              @ write to MDREFR 
    
    mov pc, lr                @ return 
@********************************************************************************************