pxa250regs.s

linux下的jtag调试软件

/*
 * pxa250.h
	from kernel/include/asm-arm/arch-pxa/pxa-regs.h
		kernel/include/asm-arm/proc-armv/ptrace.h
 *
 * Copyright (C) 2001 MIZI Research, Inc.
 *
 * Author: Yong-iL Joh <[e-mail]>
 * Date  : $Date: 2003/02/03 15:24:40 $ 
 *
 * $Revision: 1.1.1.1 $
 *
   Mon May 23 2002 Yong-iL Joh <[e-mail]>
   - initial
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 * 
 * stolen by Julien Pilet.
 */

#ifndef _PXA250REGS_H_
#define _PXA250REGS_H_


#define __REG(a) a

#define USR26_MODE	0x00
#define FIQ26_MODE	0x01
#define IRQ26_MODE	0x02
#define SVC26_MODE	0x03
#define USR_MODE	0x10
#define FIQ_MODE	0x11
#define IRQ_MODE	0x12
#define SVC_MODE	0x13
#define ABT_MODE	0x17
#define UND_MODE	0x1b
#define DBG_MODE	0b10101
#define SYSTEM_MODE	0x1f
#define MODE_MASK	0x1f
#define F_BIT		0x40
#define I_BIT		0x80
#define CC_V_BIT	(1 << 28)
#define CC_C_BIT	(1 << 29)
#define CC_Z_BIT	(1 << 30)
#define CC_N_BIT	(1 << 31)

/* for MMU */
#define CP15_1_MMU	(1 << 0)	/* MMU */
#define CP15_1_ALIGN	(1 << 1)	/* alignment fault */
#define CP15_1_DCACHE	(1 << 2)	/* Data Cache */
#define CP15_1_NOP	0x78		/* Read/Write as 0b1111 */
#define CP15_1_SYSP	(1 << 8)	/* System protection */
#define CP15_1_ROMP	(1 << 9)	/* ROM protection */
#define CP15_1_BTB	(1 << 11)	/* Branch Target Buffer */
#define CP15_1_ICACHE	(1 << 12)	/* Instruction Cache */
#define CP15_1_VECTREL	(1 << 13)	/* Exception Vector Relocation */

/*
 * PXA Chip selects
 */

#define PXA_CS0_PHYS	0x00000000
#define PXA_CS1_PHYS	0x04000000
#define PXA_CS2_PHYS	0x08000000
#define PXA_CS3_PHYS	0x0C000000
#define PXA_CS4_PHYS	0x10000000
#define PXA_CS5_PHYS	0x14000000


/*
 * UARTs
 */

#define FFUART_BASE	0x40100000
#define BTUART_BASE	0x40200000
#define STUART_BASE	0x40700000
#define UART_RBR	0x00	/* Receive Buffer Register (read only) */
#define UART_THR	0x00	/* Transmit Holding Register (write only) */
#define UART_IER	0x04	/* Interrupt Enable Register */
#define UART_IIR	0x08	/* Interrupt ID Register (read only) */
#define UART_FCR	0x08	/* FIFO Control Register (write only) */
#define UART_LCR	0x0C	/* Line Control Register */
#define UART_MCR	0x10	/* Modem Control Register */
#define UART_LSR	0x14	/* Line Status Register (read only) */
#define UART_SPR	0x1C	/* Scratch Pad Register */
#define UART_ISR	0x20	/* Infrared Selection Register */
#define UART_DLL	0x00	/* Divisor Latch Low Register (DLAB = 1) */
#define UART_DLH	0x04	/* Divisor Latch High Register (DLAB = 1) */

/* The interrupt enable register bits. */
#define SIO_IER_RAVIE   0x01	/* enable received data available irq */
#define SIO_IER_TIE	0x02	/* enable transmit data request interrupt */
#define SIO_IER_RLSE	0x04	/* enable receiver line status irq */
#define SIO_IER_MIE	0x08	/* enable modem status interrupt */
#define SIO_IER_RTOIE	0x10	/* enable Rx timeout interrupt */
#define SIO_IER_NRZE	0x20	/* enable NRZ coding */
#define SIO_IER_UUE	0x40	/* enable the UART unit */
#define SIO_IER_DMAE	0x80	/* enable DMA requests */

/* The interrupt identification register bits. */
#define SIO_IIR_IP	0x01 	/* 0 if interrupt pending */
#define SIO_IIR_ID_MASK	0xff 	/* mask for interrupt ID bits */
#define ISR_Tx		0x02
#define ISR_Rx		0x04

/* The line status register bits. */
#define SIO_LSR_DR	0x01	/* data ready */
#define SIO_LSR_OE	0x02	/* overrun error */
#define SIO_LSR_PE	0x04	/* parity error */
#define SIO_LSR_FE	0x08	/* framing error */
#define SIO_LSR_BI	0x10	/* break interrupt */
#define SIO_LSR_THRE	0x20	/* transmitter holding register empty */
#define SIO_LSR_TEMT	0x40	/* transmitter holding and Tx shift registers empty */
#define SIO_LSR_ERR	0x80	/* any error condition (FIFOE) */

/* The modem status register bits. */
#define SIO_MSR_DCTS	0x01	/* delta clear to send */
#define SIO_MSR_DDSR	0x02	/* delta data set ready */
#define SIO_MSR_TERI	0x04	/* trailing edge ring indicator */
#define SIO_MSR_DDCD	0x08	/* delta data carrier detect */
#define SIO_MSR_CTS	0x10	/* clear to send */
#define SIO_MSR_DSR	0x20	/* data set ready */
#define SIO_MSR_RI	0x40	/* ring indicator */
#define SIO_MSR_DCD	0x80	/* data carrier detect */

/* The line control register bits. */
#define SIO_LCR_WLS0	0x01 	/* word length select bit 0 */
#define SIO_LCR_WLS1	0x02 	/* word length select bit 1 */
#define SIO_LCR_STB	0x04 	/* number of stop bits */
#define SIO_LCR_PEN	0x08 	/* parity enable */
#define SIO_LCR_EPS	0x10 	/* even parity select */
#define SIO_LCR_SP	0x20 	/* stick parity */
#define SIO_LCR_SB	0x40 	/* set break */
#define SIO_LCR_DLAB	0x80 	/* divisor latch access bit */

/* The FIFO control register */
#define SIO_FCR_FCR0	0x01 	/* enable xmit and rcvr fifos */
#define SIO_FCR_FCR1	0x02 	/* clear RCVR FIFO */
#define SIO_FCR_FCR2	0x04 	/* clear XMIT FIFO */
#define SIO_FCR_ITL0	0x40 	/* Interrupt trigger level (ITL) bit 0 */
#define SIO_FCR_ITL1	0x80 	/* Interrupt trigger level (ITL) bit 1 */
#define SIO_FCR_ITL_1BYTE	0x00	/* 1 byte triggers interrupt */

/* Full Function UART (FFUART) */
#define FFUART	FFRBR
#define FFRBR	__REG(0x40100000)  /* Receive Buffer Register (read only) */
#define FFTHR	__REG(0x40100000)  /* Transmit Holding Register (write only) */
#define FFIER	__REG(0x40100004)  /* Interrupt Enable Register */
#define FFIIR	__REG(0x40100008)  /* Interrupt ID Register (read only) */
#define FFFCR	__REG(0x40100008)  /* FIFO Control Register (write only) */
#define FFLCR	__REG(0x4010000C)  /* Line Control Register */
#define FFMCR	__REG(0x40100010)  /* Modem Control Register */
#define FFLSR	__REG(0x40100014)  /* Line Status Register (read only) */
#define FFMSR	__REG(0x40100018)  /* Modem Status Register (read only) */
#define FFSPR	__REG(0x4010001C)  /* Scratch Pad Register */
#define FFISR	__REG(0x40100020)  /* Infrared Selection Register */
#define FFDLL	__REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) */
#define FFDLH	__REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) */

/* Bluetooth UART (BTUART) */
#define BTUART	BTRBR
#define BTRBR	__REG(0x40200000)  /* Receive Buffer Register (read only) */
#define BTTHR	__REG(0x40200000)  /* Transmit Holding Register (write only) */
#define BTIER	__REG(0x40200004)  /* Interrupt Enable Register */
#define BTIIR	__REG(0x40200008)  /* Interrupt ID Register (read only) */
#define BTFCR	__REG(0x40200008)  /* FIFO Control Register (write only) */
#define BTLCR	__REG(0x4020000C)  /* Line Control Register */
#define BTMCR	__REG(0x40200010)  /* Modem Control Register */
#define BTLSR	__REG(0x40200014)  /* Line Status Register (read only) */
#define BTMSR	__REG(0x40200018)  /* Modem Status Register (read only) */
#define BTSPR	__REG(0x4020001C)  /* Scratch Pad Register */
#define BTISR	__REG(0x40200020)  /* Infrared Selection Register */
#define BTDLL	__REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) */
#define BTDLH	__REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) */

/* Standard UART (STUART) */
#define STUART	STRBR
#define STRBR	__REG(0x40700000)  /* Receive Buffer Register (read only) */
#define STTHR	__REG(0x40700000)  /* Transmit Holding Register (write only) */
#define STIER	__REG(0x40700004)  /* Interrupt Enable Register */
#define STIIR	__REG(0x40700008)  /* Interrupt ID Register (read only) */
#define STFCR	__REG(0x40700008)  /* FIFO Control Register (write only) */
#define STLCR	__REG(0x4070000C)  /* Line Control Register */
#define STMCR	__REG(0x40700010)  /* Modem Control Register */
#define STLSR	__REG(0x40700014)  /* Line Status Register (read only) */
#define STMSR	__REG(0x40700018)  /* Reserved */
#define STSPR	__REG(0x4070001C)  /* Scratch Pad Register */
#define STISR	__REG(0x40700020)  /* Infrared Selection Register */
#define STDLL	__REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) */
#define STDLH	__REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) */


/*
 * Real Time Clock
 */

#define RCNR		__REG(0x40900000)  /* RTC Count Register */
#define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
#define RTSR		__REG(0x40900008)  /* RTC Status Register */
#define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */

#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */

/*
 * OS Timer & Match Registers
 */

#define OSMR0		__REG(0x40A00000)  /* */
#define OSMR1		__REG(0x40A00004)  /* */
#define OSMR2		__REG(0x40A00008)  /* */
#define OSMR3		__REG(0x40A0000C)  /* */
#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */
#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */
#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */

#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
#define OSSR_M0		(1 << 0)	/* Match status channel 0 */

#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */

#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */


/*
 * Interrupt Controller
 */

#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */


/*
 * General Purpose I/O
 */

#define PXA250_GPIO_BASE	0x40E00000
#define GPSR0_OFFSET	0x18	/* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1_OFFSET	0x1C	/* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2_OFFSET	0x20	/* GPIO Pin Output Set Register GPIO<80:64> */
#define GPCR0_OFFSET	0x24	/* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1_OFFSET	0x28	/* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2_OFFSET	0x2C	/* GPIO Pin Output Clear Register GPIO <80:64> */
#define GPDR0_OFFSET	0x0C	/* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1_OFFSET	0x10	/* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2_OFFSET	0x14	/* GPIO Pin Direction Register GPIO<80:64> */
#define GAFR0_L_OFFSET	0x54	/* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U_OFFSET	0x58	/* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L_OFFSET	0x5C	/* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U_OFFSET	0x60	/* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L_OFFSET	0x64	/* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U_OFFSET	0x68	/* GPIO Alternate Function Select Register GPIO 80 */

#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */

#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */

#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */